mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 09:05:32 +00:00
start implementing support for intel le based logic devices
This commit is contained in:
Artur Swiderski
parent
c403c984dd
commit
36bd075865
34 changed files with 3058 additions and 0 deletions
18
tests/arch/intel_le/add_sub.ys
Normal file
18
tests/arch/intel_le/add_sub.ys
Normal file
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@ -0,0 +1,18 @@
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read_verilog ../common/add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
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design -reset
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read_verilog ../common/add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
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94
tests/arch/intel_le/adffs.ys
Normal file
94
tests/arch/intel_le/adffs.ys
Normal file
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@ -0,0 +1,94 @@
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read_verilog ../common/adffs.v
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design -save read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
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design -load read
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hierarchy -top adff
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adff # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -load read
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hierarchy -top adffn
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd adffn # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 1 t:MISTRAL_ALUT2
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select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
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design -load read
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hierarchy -top dffs
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 1 t:MISTRAL_ALUT2
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select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
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design -load read
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hierarchy -top ndffnr
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
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6
tests/arch/intel_le/blockram.ys
Normal file
6
tests/arch/intel_le/blockram.ys
Normal file
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@ -0,0 +1,6 @@
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
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synth_intel_le -family cyclonev
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cd sync_ram_sdp
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select -assert-count 1 t:MISTRAL_M10K
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select -assert-none t:MISTRAL_M10K %% t:* %D
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27
tests/arch/intel_le/counter.ys
Normal file
27
tests/arch/intel_le/counter.ys
Normal file
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@ -0,0 +1,27 @@
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read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -async2sync -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 8 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
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design -reset
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read_verilog ../common/counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -async2sync -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:MISTRAL_NOT
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select -assert-count 8 t:MISTRAL_ALUT_ARITH
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select -assert-count 8 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
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43
tests/arch/intel_le/dffs.ys
Normal file
43
tests/arch/intel_le/dffs.ys
Normal file
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@ -0,0 +1,43 @@
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read_verilog ../common/dffs.v
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design -save read
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hierarchy -top dff
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -load read
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hierarchy -top dff
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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design -load read
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hierarchy -top dffe
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proc
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equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_FF
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select -assert-none t:MISTRAL_FF %% t:* %D
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44
tests/arch/intel_le/fsm.ys
Normal file
44
tests/arch/intel_le/fsm.ys
Normal file
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@ -0,0 +1,44 @@
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read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev
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async2sync
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 6 t:MISTRAL_FF
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select -assert-max 1 t:MISTRAL_NOT
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select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
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select -assert-max 1 t:MISTRAL_ALUT3
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select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
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select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
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select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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design -reset
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read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx
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async2sync
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 6 t:MISTRAL_FF
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select -assert-max 1 t:MISTRAL_NOT
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select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
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select -assert-max 2 t:MISTRAL_ALUT3 # Clang returns 2, GCC returns 1
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select -assert-max 2 t:MISTRAL_ALUT4 # Clang returns 0, GCC returns 1
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select -assert-max 6 t:MISTRAL_ALUT5 # Clang returns 5, GCC returns 4
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select -assert-max 2 t:MISTRAL_ALUT6 # Clang returns 1, GCC returns 2
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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25
tests/arch/intel_le/logic.ys
Normal file
25
tests/arch/intel_le/logic.ys
Normal file
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@ -0,0 +1,25 @@
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read_verilog ../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 6 t:MISTRAL_ALUT2
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select -assert-count 2 t:MISTRAL_ALUT4
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
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design -reset
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read_verilog ../common/logic.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 6 t:MISTRAL_ALUT2
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select -assert-count 2 t:MISTRAL_ALUT4
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
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41
tests/arch/intel_le/lutram.ys
Normal file
41
tests/arch/intel_le/lutram.ys
Normal file
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@ -0,0 +1,41 @@
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v -map +/intel_le/common/mem_sim.v synth_intel_le -family cyclonev -nobram
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 16 t:MISTRAL_MLAB
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 2 t:MISTRAL_ALUT2
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select -assert-count 8 t:MISTRAL_ALUT3
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select -assert-count 17 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v -map +/intel_le/common/mem_sim.v synth_intel_le -family cyclonev -nobram
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 16 t:MISTRAL_MLAB
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select -assert-count 1 t:MISTRAL_NOT
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select -assert-count 2 t:MISTRAL_ALUT2
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select -assert-count 8 t:MISTRAL_ALUT3
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select -assert-count 17 t:MISTRAL_FF
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select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
|
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60
tests/arch/intel_le/mul.ys
Normal file
60
tests/arch/intel_le/mul.ys
Normal file
|
|
@ -0,0 +1,60 @@
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
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cd top # Constrain all select calls below inside the top module
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|
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select -assert-count 1 t:MISTRAL_MUL9X9
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select -assert-none t:MISTRAL_MUL9X9 %% t:* %D
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|
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# Cyclone 10 GX does not have 9x9 multipliers.
|
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|
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
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hierarchy -top top
|
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proc
|
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equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
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cd top # Constrain all select calls below inside the top module
|
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|
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select -assert-count 1 t:MISTRAL_MUL18X18
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select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
|
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|
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design -reset
|
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
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hierarchy -top top
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proc
|
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equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclone10gx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 1 t:MISTRAL_MUL18X18
|
||||
select -assert-none t:MISTRAL_MUL18X18 %% t:* %D
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclonev # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 1 t:MISTRAL_MUL27X27
|
||||
select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/mul.v
|
||||
chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
|
||||
hierarchy -top top
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/dsp_sim.v synth_intel_le -family cyclone10gx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 1 t:MISTRAL_MUL27X27
|
||||
select -assert-none t:MISTRAL_MUL27X27 %% t:* %D
|
||||
88
tests/arch/intel_le/mux.ys
Normal file
88
tests/arch/intel_le/mux.ys
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
read_verilog ../common/mux.v
|
||||
design -save read
|
||||
|
||||
|
||||
hierarchy -top mux2
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux2 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MISTRAL_ALUT3
|
||||
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux2
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux2 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MISTRAL_ALUT3
|
||||
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux4
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux4 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MISTRAL_ALUT6
|
||||
select -assert-none t:MISTRAL_ALUT6 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux4
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux4 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MISTRAL_ALUT6
|
||||
select -assert-none t:MISTRAL_ALUT6 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux8
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux8 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MISTRAL_ALUT3
|
||||
select -assert-count 2 t:MISTRAL_ALUT6
|
||||
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux8
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux8 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MISTRAL_ALUT3
|
||||
select -assert-count 2 t:MISTRAL_ALUT6
|
||||
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux16
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclonev # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux16 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MISTRAL_ALUT3
|
||||
select -assert-max 2 t:MISTRAL_ALUT5
|
||||
select -assert-max 5 t:MISTRAL_ALUT6
|
||||
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
|
||||
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux16
|
||||
proc
|
||||
equiv_opt -assert -map +/intel_le/common/alm_sim.v synth_intel_le -family cyclone10gx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux16 # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:MISTRAL_ALUT3
|
||||
select -assert-count 2 t:MISTRAL_ALUT5
|
||||
select -assert-count 4 t:MISTRAL_ALUT6
|
||||
|
||||
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
|
||||
26
tests/arch/intel_le/quartus_ice.ys
Normal file
26
tests/arch/intel_le/quartus_ice.ys
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
read_verilog <<EOT
|
||||
// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
|
||||
// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
|
||||
module top();
|
||||
(* keep *) wire [31:0] \a[10] ;
|
||||
(* keep *) wire b;
|
||||
assign b = \a[10] [31];
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
synth_intel_le -family cyclonev -quartus
|
||||
select -assert-none w:*[* w:*]*
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
|
||||
// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
|
||||
module top();
|
||||
(* keep *) wire [31:0] \a[10] ;
|
||||
(* keep *) wire b;
|
||||
assign b = \a[10] [31];
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
synth_intel_le -family cyclone10gx -quartus
|
||||
select -assert-none w:*[* w:*]*
|
||||
4
tests/arch/intel_le/run-test.sh
Executable file
4
tests/arch/intel_le/run-test.sh
Executable file
|
|
@ -0,0 +1,4 @@
|
|||
#!/usr/bin/env bash
|
||||
set -eu
|
||||
source ../../gen-tests-makefile.sh
|
||||
run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
|
||||
21
tests/arch/intel_le/shifter.ys
Normal file
21
tests/arch/intel_le/shifter.ys
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
read_verilog ../common/shifter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclonev # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 8 t:MISTRAL_FF
|
||||
select -assert-none t:MISTRAL_FF %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/shifter.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
flatten
|
||||
equiv_opt -async2sync -assert -map +/intel_le/common/alm_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cyclone10gx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd top # Constrain all select calls below inside the top module
|
||||
select -assert-count 8 t:MISTRAL_FF
|
||||
select -assert-none t:MISTRAL_FF %% t:* %D
|
||||
27
tests/arch/intel_le/tribuf.ys
Normal file
27
tests/arch/intel_le/tribuf.ys
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
read_verilog ../common/tribuf.v
|
||||
hierarchy -top tristate
|
||||
proc
|
||||
tribuf
|
||||
flatten
|
||||
synth
|
||||
equiv_opt -assert -map +/simcells.v synth_intel_le -family cyclonev # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd tristate # Constrain all select calls below inside the top module
|
||||
#Internal cell type used. Need support it.
|
||||
select -assert-count 1 t:$_TBUF_
|
||||
select -assert-none t:$_TBUF_ %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/tribuf.v
|
||||
hierarchy -top tristate
|
||||
proc
|
||||
tribuf
|
||||
flatten
|
||||
synth
|
||||
equiv_opt -assert -map +/simcells.v synth_intel_le -family cyclone10gx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd tristate # Constrain all select calls below inside the top module
|
||||
#Internal cell type used. Need support it.
|
||||
select -assert-count 1 t:$_TBUF_
|
||||
select -assert-none t:$_TBUF_ %% t:* %D
|
||||
Loading…
Add table
Add a link
Reference in a new issue