3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 03:45:52 +00:00

start implementing support for intel le based logic devices

This commit is contained in:
Artur Swiderski 2020-10-10 19:08:54 +02:00
parent c403c984dd
commit 36bd075865
34 changed files with 3058 additions and 0 deletions

View file

@ -0,0 +1,11 @@
// After performing sequential synthesis, map the synchronous flops back to
// standard MISTRAL_FF flops.
module $__MISTRAL_FF_SYNCONLY (
input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,
output reg Q
);
MISTRAL_FF _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ACLR(1'b1), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
endmodule