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start implementing support for intel le based logic devices

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This commit is contained in:
Artur Swiderski 2020-10-10 19:08:54 +02:00
parent c403c984dd
commit 36bd075865
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18
techlibs/intel_le/common/abc9_map.v Normal file
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// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-clear as boxes, this is because ABC9
// doesn't support asynchronous-clear flops in sequential synthesis.
module MISTRAL_FF(
input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA,
output reg Q
);
parameter _TECHMAP_CONSTMSK_ACLR_ = 1'b0;
// If the async-clear is constant, we assume it's disabled.
if (_TECHMAP_CONSTMSK_ACLR_ != 1'b0)
$__MISTRAL_FF_SYNCONLY _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
else
wire _TECHMAP_FAIL_ = 1;
endmodule