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techmap: sort celltypeMap as it determines techmap order

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Eddie Hung 2020-04-20 20:56:38 -07:00 committed by Alberto Gonzalez
parent ce62d0751a
commit 36bb201dd9
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GPG key ID: 8395A8BA109708B2
1 changed files with 5 additions and 1 deletions
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6
passes/techmap/techmap.cc
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@ -1313,11 +1313,13 @@ struct TechmapPass : public Pass {
celltypeMap[RTLIL::escape_id(q)].insert(module->name); celltypeMap[RTLIL::escape_id(q)].insert(module->name);
free(p); free(p);
} else { } else {
std::string module_name = module->name.begins_with("\\$") ? IdString module_name = module->name.begins_with("\\$") ?
module->name.substr(1) : module->name.str(); module->name.substr(1) : module->name.str();
celltypeMap[module_name].insert(module->name); celltypeMap[module_name].insert(module->name);
} }
} }
for (auto &i : celltypeMap)
i.second.sort(RTLIL::sort_by_id_str());
for (auto module : design->modules()) for (auto module : design->modules())
worker.module_queue.insert(module); worker.module_queue.insert(module);
@ -1389,6 +1391,8 @@ struct FlattenPass : public Pass {
dict<IdString, pool<IdString>> celltypeMap; dict<IdString, pool<IdString>> celltypeMap;
for (auto module : design->modules()) for (auto module : design->modules())
celltypeMap[module->name].insert(module->name); celltypeMap[module->name].insert(module->name);
for (auto &i : celltypeMap)
i.second.sort(RTLIL::sort_by_id_str());
RTLIL::Module *top_mod = nullptr; RTLIL::Module *top_mod = nullptr;
if (design->full_selection()) if (design->full_selection())