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coolrunner2: Initial mapping of latches
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@ -94,3 +94,43 @@ module FDCP_N (C, PRE, CLR, D, Q);
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Q <= D;
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end
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endmodule
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module LDCP (G, PRE, CLR, D, Q);
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parameter INIT = 0;
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input G, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @* begin
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if (CLR == 1)
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Q <= 0;
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else if (G == 1)
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Q <= D;
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else if (PRE == 1)
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Q <= 1;
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end
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endmodule
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module LDCP_N (G, PRE, CLR, D, Q);
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parameter INIT = 0;
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input G, PRE, CLR, D;
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output reg Q;
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initial begin
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Q <= INIT;
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end
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always @* begin
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if (CLR == 1)
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Q <= 0;
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else if (G == 0)
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Q <= D;
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else if (PRE == 1)
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Q <= 1;
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end
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endmodule
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