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Added support for non-const === and !== (for miter circuits)

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This commit is contained in:
Clifford Wolf 2013-12-27 14:20:15 +01:00
parent ecc30255ba
commit 369bf81a70
10 changed files with 128 additions and 20 deletions
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12
passes/opt/opt_const.cc
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@ -144,7 +144,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
#endif
}
if (cell->type == "$eq" || cell->type == "$ne")
if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
{
RTLIL::SigSpec a = cell->connections["\\A"];
RTLIL::SigSpec b = cell->connections["\\B"];
@ -160,10 +160,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assert(a.chunks.size() == b.chunks.size());
for (size_t i = 0; i < a.chunks.size(); i++) {
if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
continue;
if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
continue;
if (cell->type == "$eq" || cell->type == "$ne") {
if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
continue;
if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
continue;
}
new_a.append(a.chunks[i]);
new_b.append(b.chunks[i]);
}