mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-08 15:13:24 +00:00
Code Activity

Added support for non-const === and !== (for miter circuits)

Browse source
This commit is contained in:
Clifford Wolf 2013-12-27 14:20:15 +01:00
parent ecc30255ba
commit 369bf81a70
10 changed files with 128 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

14
backends/verilog/verilog_backend.cc
View file

@ -506,12 +506,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
HANDLE_BINOP("$sshl", "<<<")
HANDLE_BINOP("$sshr", ">>>")
HANDLE_BINOP("$lt", "<")
HANDLE_BINOP("$le", "<=")
HANDLE_BINOP("$eq", "==")
HANDLE_BINOP("$ne", "!=")
HANDLE_BINOP("$ge", ">=")
HANDLE_BINOP("$gt", ">")
HANDLE_BINOP("$lt", "<")
HANDLE_BINOP("$le", "<=")
HANDLE_BINOP("$eq", "==")
HANDLE_BINOP("$ne", "!=")
HANDLE_BINOP("$eqx", "===")
HANDLE_BINOP("$nex", "!==")
HANDLE_BINOP("$ge", ">=")
HANDLE_BINOP("$gt", ">")
HANDLE_BINOP("$add", "+")
HANDLE_BINOP("$sub", "-")