mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

More fixes in ternary op sign handling

Browse source
This commit is contained in:
Clifford Wolf 2013-07-12 13:13:04 +02:00
parent ded769c98c
commit 3650fd7fbe
2 changed files with 11 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
frontends/ast/genrtlil.cc
View file

@ -998,6 +998,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate multiplexer for ternary operator (aka ?:-operator) // generate multiplexer for ternary operator (aka ?:-operator)
case AST_TERNARY: case AST_TERNARY:
{ {
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
RTLIL::SigSpec cond = children[0]->genRTLIL(); RTLIL::SigSpec cond = children[0]->genRTLIL();
RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);

8
tests/simple/vloghammer.v
View file

@ -65,3 +65,11 @@ module test09(a, b, c, y);
assign y = a ? b : c; assign y = a ? b : c;
endmodule endmodule
module test10(a, b, c, y);
input a;
input signed [1:0] b;
input signed [2:0] c;
output y;
assign y = ^(a ? b : c);
endmodule