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Docs: Updates from @povik comments

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Krystine Sherwin 2024-03-05 05:57:27 +13:00
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docs/source/yosys_internals/index.rst
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@ -15,6 +15,8 @@ Yosys can synthesize a large subset of Verilog 2005 and has been tested with a
wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
`openMSP430 CPU`_, the `OpenCores I2C master`_, and the `k68 CPU`_. `openMSP430 CPU`_, the `OpenCores I2C master`_, and the `k68 CPU`_.
.. todo:: add RISC-V core example
.. _OpenRISC 1200 CPU: https://github.com/openrisc/or1200 .. _OpenRISC 1200 CPU: https://github.com/openrisc/or1200
.. _openMSP430 CPU: http://opencores.org/projects/openmsp430 .. _openMSP430 CPU: http://opencores.org/projects/openmsp430
@ -23,13 +25,11 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
.. _k68 CPU: http://opencores.org/projects/k68 .. _k68 CPU: http://opencores.org/projects/k68
As of this writing, a Yosys VHDL frontend is in development. Yosys is written in C++, targeting C++11 at minimum. This chapter describes some
of the fundamental Yosys data structures. For the sake of simplicity the C++
Yosys is written in C++ (using some features from the new C++11 standard). This type names used in the Yosys implementation are used in this chapter, even
chapter describes some of the fundamental Yosys data structures. For the sake of though the chapter only explains the conceptual idea behind it and can be used
simplicity the C++ type names used in the Yosys implementation are used in this as reference to implement a similar system in any language.
chapter, even though the chapter only explains the conceptual idea behind it and
can be used as reference to implement a similar system in any language.
.. toctree:: .. toctree::
:maxdepth: 3 :maxdepth: 3