mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Replaced depricated NEW_WIRE macro with module->addWire() calls

Browse source
This commit is contained in:
Clifford Wolf 2014-07-21 12:41:29 +02:00
parent 1d88f1cf9f
commit 361e0d62ff
4 changed files with 22 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

20
frontends/liberty/liberty.cc
View file

@ -58,7 +58,7 @@ static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
cell->name = NEW_ID; cell->name = NEW_ID;
cell->type = "$_INV_"; cell->type = "$_INV_";
cell->connections["\\A"] = A; cell->connections["\\A"] = A;
cell->connections["\\Y"] = NEW_WIRE(module, 1); cell->connections["\\Y"] = module->addWire(NEW_ID);
module->add(cell); module->add(cell);
return cell->connections["\\Y"]; return cell->connections["\\Y"];
} }
@ -70,7 +70,7 @@ static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, R
cell->type = "$_XOR_"; cell->type = "$_XOR_";
cell->connections["\\A"] = A; cell->connections["\\A"] = A;
cell->connections["\\B"] = B; cell->connections["\\B"] = B;
cell->connections["\\Y"] = NEW_WIRE(module, 1); cell->connections["\\Y"] = module->addWire(NEW_ID);
module->add(cell); module->add(cell);
return cell->connections["\\Y"]; return cell->connections["\\Y"];
} }
@ -82,7 +82,7 @@ static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, R
cell->type = "$_AND_"; cell->type = "$_AND_";
cell->connections["\\A"] = A; cell->connections["\\A"] = A;
cell->connections["\\B"] = B; cell->connections["\\B"] = B;
cell->connections["\\Y"] = NEW_WIRE(module, 1); cell->connections["\\Y"] = module->addWire(NEW_ID);
module->add(cell); module->add(cell);
return cell->connections["\\Y"]; return cell->connections["\\Y"];
} }
@ -94,7 +94,7 @@ static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RT
cell->type = "$_OR_"; cell->type = "$_OR_";
cell->connections["\\A"] = A; cell->connections["\\A"] = A;
cell->connections["\\B"] = B; cell->connections["\\B"] = B;
cell->connections["\\Y"] = NEW_WIRE(module, 1); cell->connections["\\Y"] = module->addWire(NEW_ID);
module->add(cell); module->add(cell);
return cell->connections["\\Y"]; return cell->connections["\\Y"];
} }
@ -370,7 +370,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
inv->name = NEW_ID; inv->name = NEW_ID;
inv->type = "$_INV_"; inv->type = "$_INV_";
inv->connections["\\A"] = clear_sig; inv->connections["\\A"] = clear_sig;
inv->connections["\\Y"] = NEW_WIRE(module, 1);; inv->connections["\\Y"] = module->addWire(NEW_ID);
module->add(inv); module->add(inv);
if (clear_polarity == true) if (clear_polarity == true)
@ -384,7 +384,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
data_gate->type = "$_AND_"; data_gate->type = "$_AND_";
data_gate->connections["\\A"] = data_sig; data_gate->connections["\\A"] = data_sig;
data_gate->connections["\\B"] = clear_negative; data_gate->connections["\\B"] = clear_negative;
data_gate->connections["\\Y"] = data_sig = NEW_WIRE(module, 1);; data_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
module->add(data_gate); module->add(data_gate);
RTLIL::Cell *enable_gate = new RTLIL::Cell; RTLIL::Cell *enable_gate = new RTLIL::Cell;
@ -392,7 +392,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_"; enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_";
enable_gate->connections["\\A"] = enable_sig; enable_gate->connections["\\A"] = enable_sig;
enable_gate->connections["\\B"] = clear_enable; enable_gate->connections["\\B"] = clear_enable;
enable_gate->connections["\\Y"] = data_sig = NEW_WIRE(module, 1);; enable_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
module->add(enable_gate); module->add(enable_gate);
} }
@ -407,7 +407,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
inv->name = NEW_ID; inv->name = NEW_ID;
inv->type = "$_INV_"; inv->type = "$_INV_";
inv->connections["\\A"] = preset_sig; inv->connections["\\A"] = preset_sig;
inv->connections["\\Y"] = NEW_WIRE(module, 1);; inv->connections["\\Y"] = module->addWire(NEW_ID);
module->add(inv); module->add(inv);
if (preset_polarity == false) if (preset_polarity == false)
@ -421,7 +421,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
data_gate->type = "$_OR_"; data_gate->type = "$_OR_";
data_gate->connections["\\A"] = data_sig; data_gate->connections["\\A"] = data_sig;
data_gate->connections["\\B"] = preset_positive; data_gate->connections["\\B"] = preset_positive;
data_gate->connections["\\Y"] = data_sig = NEW_WIRE(module, 1);; data_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
module->add(data_gate); module->add(data_gate);
RTLIL::Cell *enable_gate = new RTLIL::Cell; RTLIL::Cell *enable_gate = new RTLIL::Cell;
@ -429,7 +429,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_"; enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_";
enable_gate->connections["\\A"] = enable_sig; enable_gate->connections["\\A"] = enable_sig;
enable_gate->connections["\\B"] = preset_enable; enable_gate->connections["\\B"] = preset_enable;
enable_gate->connections["\\Y"] = data_sig = NEW_WIRE(module, 1);; enable_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
module->add(enable_gate); module->add(enable_gate);
} }

3
kernel/rtlil.h
View file

@ -141,9 +141,6 @@ namespace RTLIL
#define NEW_ID \ #define NEW_ID \
RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__)
#define NEW_WIRE(_mod, _width) \
(_mod)->addWire(NEW_ID, _width)
template <typename T> struct sort_by_name { template <typename T> struct sort_by_name {
bool operator()(T *a, T *b) const { bool operator()(T *a, T *b) const {
return a->name < b->name; return a->name < b->name;

20
passes/proc/proc_dff.cc
View file

@ -80,7 +80,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width);
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_low_signals; cell->connections["\\A"] = sync_low_signals;
cell->connections["\\Y"] = sync_low_signals = NEW_WIRE(mod, 1); cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID);
mod->add(cell); mod->add(cell);
} }
@ -92,7 +92,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.width);
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_low_signals; cell->connections["\\A"] = sync_low_signals;
cell->connections["\\Y"] = NEW_WIRE(mod, 1); cell->connections["\\Y"] = mod->addWire(NEW_ID);
sync_high_signals.append(cell->connections["\\Y"]); sync_high_signals.append(cell->connections["\\Y"]);
mod->add(cell); mod->add(cell);
} }
@ -105,7 +105,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.width); cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.width);
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_high_signals; cell->connections["\\A"] = sync_high_signals;
cell->connections["\\Y"] = sync_high_signals = NEW_WIRE(mod, 1); cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID);
mod->add(cell); mod->add(cell);
} }
@ -116,7 +116,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.width); inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.width);
inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.width); inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.width);
inv_cell->connections["\\A"] = sync_value; inv_cell->connections["\\A"] = sync_value;
inv_cell->connections["\\Y"] = sync_value_inv = NEW_WIRE(mod, sig_d.width); inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.width);
mod->add(inv_cell); mod->add(inv_cell);
RTLIL::Cell *mux_set_cell = new RTLIL::Cell; RTLIL::Cell *mux_set_cell = new RTLIL::Cell;
@ -126,7 +126,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
mux_set_cell->connections["\\A"] = sig_sr_set; mux_set_cell->connections["\\A"] = sig_sr_set;
mux_set_cell->connections["\\B"] = sync_value; mux_set_cell->connections["\\B"] = sync_value;
mux_set_cell->connections["\\S"] = sync_high_signals; mux_set_cell->connections["\\S"] = sync_high_signals;
mux_set_cell->connections["\\Y"] = sig_sr_set = NEW_WIRE(mod, sig_d.width); mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.width);
mod->add(mux_set_cell); mod->add(mux_set_cell);
RTLIL::Cell *mux_clr_cell = new RTLIL::Cell; RTLIL::Cell *mux_clr_cell = new RTLIL::Cell;
@ -136,7 +136,7 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
mux_clr_cell->connections["\\A"] = sig_sr_clr; mux_clr_cell->connections["\\A"] = sig_sr_clr;
mux_clr_cell->connections["\\B"] = sync_value_inv; mux_clr_cell->connections["\\B"] = sync_value_inv;
mux_clr_cell->connections["\\S"] = sync_high_signals; mux_clr_cell->connections["\\S"] = sync_high_signals;
mux_clr_cell->connections["\\Y"] = sig_sr_clr = NEW_WIRE(mod, sig_d.width); mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.width);
mod->add(mux_clr_cell); mod->add(mux_clr_cell);
} }
@ -168,9 +168,9 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
std::stringstream sstr; std::stringstream sstr;
sstr << "$procdff$" << (RTLIL::autoidx++); sstr << "$procdff$" << (RTLIL::autoidx++);
RTLIL::SigSpec sig_set_inv = NEW_WIRE(mod, sig_in.width); RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.width);
RTLIL::SigSpec sig_sr_set = NEW_WIRE(mod, sig_in.width); RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.width);
RTLIL::SigSpec sig_sr_clr = NEW_WIRE(mod, sig_in.width); RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.width);
RTLIL::Cell *inv_set = new RTLIL::Cell; RTLIL::Cell *inv_set = new RTLIL::Cell;
inv_set->name = NEW_ID; inv_set->name = NEW_ID;
@ -315,7 +315,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
{ {
sync_level = new RTLIL::SyncRule; sync_level = new RTLIL::SyncRule;
sync_level->type = RTLIL::SyncType::ST1; sync_level->type = RTLIL::SyncType::ST1;
sync_level->signal = NEW_WIRE(mod, 1); sync_level->signal = mod->addWire(NEW_ID);
sync_level->actions.push_back(RTLIL::SigSig(sig, rstval)); sync_level->actions.push_back(RTLIL::SigSig(sig, rstval));
free_sync_level = true; free_sync_level = true;

4
passes/techmap/hilomap.cc
View file

@ -34,7 +34,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
for (auto &c : sig.chunks) { for (auto &c : sig.chunks) {
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi.width == 0) { if (!singleton_mode || last_hi.width == 0) {
last_hi = RTLIL::SigChunk(NEW_WIRE(module, 1)); last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
RTLIL::Cell *cell = new RTLIL::Cell; RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID; cell->name = NEW_ID;
cell->type = RTLIL::escape_id(hicell_celltype); cell->type = RTLIL::escape_id(hicell_celltype);
@ -45,7 +45,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
} }
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) { if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) {
if (!singleton_mode || last_lo.width == 0) { if (!singleton_mode || last_lo.width == 0) {
last_lo = RTLIL::SigChunk(NEW_WIRE(module, 1)); last_lo = RTLIL::SigChunk(module->addWire(NEW_ID));
RTLIL::Cell *cell = new RTLIL::Cell; RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID; cell->name = NEW_ID;
cell->type = RTLIL::escape_id(locell_celltype); cell->type = RTLIL::escape_id(locell_celltype);