mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-28 17:08:46 +00:00
Code Activity

Replaced depricated NEW_WIRE macro with module->addWire() calls

Browse source
This commit is contained in:
Clifford Wolf 2014-07-21 12:41:29 +02:00
parent 1d88f1cf9f
commit 361e0d62ff
4 changed files with 22 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/techmap/hilomap.cc
View file

@ -34,7 +34,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
for (auto &c : sig.chunks) {
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi.width == 0) {
last_hi = RTLIL::SigChunk(NEW_WIRE(module, 1));
last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(hicell_celltype);
@ -45,7 +45,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
}
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) {
if (!singleton_mode || last_lo.width == 0) {
last_lo = RTLIL::SigChunk(NEW_WIRE(module, 1));
last_lo = RTLIL::SigChunk(module->addWire(NEW_ID));
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(locell_celltype);