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https://github.com/YosysHQ/yosys
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Fix pop order.
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parent
4b657938dc
commit
3611fca18b
1 changed files with 21 additions and 15 deletions
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@ -160,8 +160,11 @@ struct CellTypes
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return cell_types.count(type) != 0;
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}
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bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const
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bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const
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{
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auto it = cell_types.find(type);
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if (it != cell_types.end())
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return it->second.outputs.count(port) != 0;
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size_t idx = type.index_;
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bool is_builtin = (enabled_cats == BITS_ALL) ? builtin_is_known(idx) : builtin_match(idx);
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if (is_builtin) {
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@ -170,14 +173,15 @@ struct CellTypes
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for (uint16_t i = 0; i < count; i++)
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if (StaticCellTypes::GeneratedData::port_outputs_ports[idx][i] == target)
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return true;
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return false;
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}
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.outputs.count(port) != 0;
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return false;
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}
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bool cell_input(const RTLIL::IdString &type, const RTLIL::IdString &port) const
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{
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auto it = cell_types.find(type);
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if (it != cell_types.end())
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return it->second.inputs.count(port) != 0;
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size_t idx = type.index_;
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bool is_builtin = (enabled_cats == BITS_ALL) ? builtin_is_known(idx) : builtin_match(idx);
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if (is_builtin) {
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@ -186,14 +190,18 @@ struct CellTypes
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for (uint16_t i = 0; i < count; i++)
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if (StaticCellTypes::GeneratedData::port_inputs_ports[idx][i] == target)
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return true;
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return false;
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}
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.inputs.count(port) != 0;
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return false;
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}
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RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const
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{
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auto it = cell_types.find(type);
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if (it != cell_types.end()) {
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bool is_input = it->second.inputs.count(port);
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bool is_output = it->second.outputs.count(port);
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return RTLIL::PortDir(is_input + is_output * 2);
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}
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size_t idx = type.index_;
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bool is_builtin = (enabled_cats == BITS_ALL) ? builtin_is_known(idx) : builtin_match(idx);
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if (is_builtin) {
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@ -209,23 +217,21 @@ struct CellTypes
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{ is_out = true; break; }
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return RTLIL::PortDir(is_in + is_out * 2);
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}
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auto it = cell_types.find(type);
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if (it == cell_types.end())
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return RTLIL::PD_UNKNOWN;
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bool is_in = it->second.inputs.count(port);
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bool is_out = it->second.outputs.count(port);
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return RTLIL::PortDir(is_in + is_out * 2);
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return RTLIL::PD_UNKNOWN;
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}
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bool cell_evaluable(const RTLIL::IdString &type) const
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{
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auto it = cell_types.find(type);
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if (it != cell_types.end())
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return it->second.is_evaluable;
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size_t idx = type.index_;
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bool is_builtin = (enabled_cats == BITS_ALL) ? builtin_is_known(idx) : builtin_match(idx);
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if (is_builtin)
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return idx < (size_t)StaticCellTypes::GEN_MAX_CELLS &&
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StaticCellTypes::GeneratedData::is_cell_evaluable[idx];
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.is_evaluable;
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return false;
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}
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static RTLIL::Const eval_not(RTLIL::Const v)
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