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Do not the 'z' modifier in format string (another win32 fix)

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This commit is contained in:
Clifford Wolf 2014-10-11 11:42:08 +02:00
parent 8263f6a74a
commit 35fbc0b35f
5 changed files with 9 additions and 9 deletions
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4
frontends/ast/ast.cc
View file

@ -267,7 +267,7 @@ void AstNode::dumpAst(FILE *f, std::string indent)
bits[i-1] == RTLIL::S1 ? '1' : bits[i-1] == RTLIL::S1 ? '1' :
bits[i-1] == RTLIL::Sx ? 'x' : bits[i-1] == RTLIL::Sx ? 'x' :
bits[i-1] == RTLIL::Sz ? 'z' : '?'); bits[i-1] == RTLIL::Sz ? 'z' : '?');
fprintf(f, "'(%zd)", bits.size()); fprintf(f, "'(%d)", GetSize(bits));
} }
if (is_input) if (is_input)
fprintf(f, " input"); fprintf(f, " input");
@ -471,7 +471,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
else if (bits.size() == 32) else if (bits.size() == 32)
fprintf(f, "%d", RTLIL::Const(bits).as_int()); fprintf(f, "%d", RTLIL::Const(bits).as_int());
else else
fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str()); fprintf(f, "%d'b %s", GetSize(bits), RTLIL::Const(bits).as_string().c_str());
break; break;
case AST_REALVALUE: case AST_REALVALUE:

2
passes/fsm/fsm_expand.cc
View file

@ -239,7 +239,7 @@ struct FsmExpand
if (merged_set.size() > 0 && !already_optimized) if (merged_set.size() > 0 && !already_optimized)
FsmData::optimize_fsm(fsm_cell, module); FsmData::optimize_fsm(fsm_cell, module);
log(" merged %zd cells into FSM.\n", merged_set.size()); log(" merged %d cells into FSM.\n", GetSize(merged_set));
} }
}; };

6
passes/fsm/fsm_recode.cc
View file

@ -41,9 +41,9 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
prefix, RTLIL::unescape_id(module->name).c_str()); prefix, RTLIL::unescape_id(module->name).c_str());
fprintf(f, "set_fsm_encoding {"); fprintf(f, "set_fsm_encoding {");
for (size_t i = 0; i < fsm_data.state_table.size(); i++) { for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
fprintf(f, " s%zd=2#", i); fprintf(f, " s%d=2#", i);
for (int j = int(fsm_data.state_table[i].bits.size())-1; j >= 0; j--) for (int j = GetSize(fsm_data.state_table[i].bits)-1; j >= 0; j--)
fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0'); fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
} }
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",

2
passes/hierarchy/hierarchy.cc
View file

@ -281,7 +281,7 @@ void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool f
delete mod; delete mod;
} }
log("Removed %zd unused modules.\n", del_modules.size()); log("Removed %d unused modules.\n", GetSize(del_modules));
} }
bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod) bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)

4
passes/opt/opt_muxtree.cc
View file

@ -174,12 +174,12 @@ struct OptMuxtreeWorker
for (auto &mi : mux2info) for (auto &mi : mux2info)
{ {
std::vector<int> live_ports; std::vector<int> live_ports;
for (size_t port_idx = 0; port_idx < mi.ports.size(); port_idx++) { for (int port_idx = 0; port_idx < GetSize(mi.ports); port_idx++) {
portinfo_t &pi = mi.ports[port_idx]; portinfo_t &pi = mi.ports[port_idx];
if (pi.enabled) { if (pi.enabled) {
live_ports.push_back(port_idx); live_ports.push_back(port_idx);
} else { } else {
log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(), log(" dead port %d/%d on %s %s.\n", port_idx+1, GetSize(mi.ports),
mi.cell->type.c_str(), mi.cell->name.c_str()); mi.cell->type.c_str(), mi.cell->name.c_str());
removed_count++; removed_count++;
} }