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Revert "Refactor to ShregmapTechXilinx7Static"
This reverts commit e1e37db860.
This commit is contained in:
Eddie Hung
parent
b6a39351f4
commit
3579d68193
1 changed files with 50 additions and 90 deletions
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@ -29,7 +29,7 @@ struct ShregmapTech
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virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
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virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
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virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
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};
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struct ShregmapOptions
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@ -71,7 +71,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech
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return true;
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}
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virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
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{
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auto D = cell->getPort("\\D");
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auto C = cell->getPort("\\C");
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@ -89,84 +89,16 @@ struct ShregmapTechGreenpak4 : ShregmapTech
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}
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cell->setParam("\\OUTA_INVERT", 0);
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return newcell;
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return false;
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}
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};
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struct ShregmapTechXilinx7Static : ShregmapTech
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{
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const ShregmapOptions &opts;
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ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/) override
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{
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if (GetSize(taps) == 1)
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return taps[0] >= opts.minlen-1;
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if (taps.back() < opts.minlen-1)
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return false;
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return true;
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}
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virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &/*taps*/) override
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{
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auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_");
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newcell->set_src_attribute(cell->get_src_attribute());
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newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
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newcell->setParam("\\INIT", cell->getParam("\\INIT"));
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if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_",
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"$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) {
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int param_clkpol = -1;
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int param_enpol = 2;
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if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0;
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else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1;
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else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
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else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
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else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
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else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
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else log_abort();
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log_assert(param_clkpol >= 0);
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newcell->setParam("\\CLKPOL", param_clkpol);
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newcell->setParam("\\ENPOL", param_enpol);
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if (cell->hasPort("\\E"))
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newcell->setPort("\\E", cell->getPort("\\E"));
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}
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else if (cell->type.in("$__SHREG_FDRE_", "$__SHREG_FDSE_", "$__SHREG_FDCE_", "$__SHREG_FDPE_")) {
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if (cell->getParam("\\IS_C_INVERTED").as_bool())
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newcell->setParam("\\CLKPOL", 0);
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else
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newcell->setParam("\\CLKPOL", 1);
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newcell->setParam("\\ENPOL", 1);
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newcell->setPort("\\E", cell->getPort("\\CE"));
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}
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else if (cell->type.in("$__SHREG_FDRE_1_", "$__SHREG_FDSE_1_", "$__SHREG_FDCE_1_", "$__SHREG_FDPE_1_")) {
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newcell->setParam("\\CLKPOL", 0);
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newcell->setPort("\\E", cell->getPort("\\CE"));
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}
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else log_abort();
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newcell->setParam("\\ENPOL", 1);
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newcell->setPort("\\C", cell->getPort("\\C"));
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newcell->setPort("\\D", cell->getPort("\\D"));
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newcell->setPort("\\Q", cell->getPort("\\Q"));
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return newcell;
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}
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};
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struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static
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struct ShregmapTechXilinx7Dynamic : ShregmapTech
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{
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dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
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const ShregmapOptions &opts;
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ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : ShregmapTechXilinx7Static(opts) {}
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ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : opts(opts) {}
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virtual void init(const Module* module, const SigMap &sigmap) override
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{
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@ -268,7 +200,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static
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return true;
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}
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virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
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{
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const auto &tap = *taps.begin();
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auto bit = tap.second;
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@ -276,24 +208,52 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static
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auto it = sigbit_to_shiftx_offset.find(bit);
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log_assert(it != sigbit_to_shiftx_offset.end());
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RTLIL::Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps);
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log_assert(newcell);
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log_assert(newcell->type == "$__SHREG_");
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newcell->type = "$__XILINX_SHREG_";
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auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_");
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newcell->set_src_attribute(cell->get_src_attribute());
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newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
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newcell->setParam("\\INIT", cell->getParam("\\INIT"));
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Cell* shiftx = std::get<0>(it->second);
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RTLIL::SigSpec l_wire;
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if (shiftx->type == "$shiftx")
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l_wire = shiftx->getPort("\\B");
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else if (shiftx->type == "$mux")
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l_wire = shiftx->getPort("\\S");
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if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_",
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"$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) {
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int param_clkpol = -1;
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int param_enpol = 2;
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if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0;
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else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1;
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else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
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else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
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else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
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else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
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else log_abort();
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log_assert(param_clkpol >= 0);
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cell->setParam("\\CLKPOL", param_clkpol);
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cell->setParam("\\ENPOL", param_enpol);
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}
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else log_abort();
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newcell->setPort("\\L", l_wire);
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newcell->setPort("\\Q", shiftx->getPort("\\Y"));
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shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
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newcell->setPort("\\C", cell->getPort("\\C"));
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newcell->setPort("\\D", cell->getPort("\\D"));
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if (cell->hasPort("\\E"))
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newcell->setPort("\\E", cell->getPort("\\E"));
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return newcell;
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Cell* shiftx = std::get<0>(it->second);
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RTLIL::SigSpec l_wire, q_wire;
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if (shiftx->type == "$shiftx") {
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l_wire = shiftx->getPort("\\B");
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q_wire = shiftx->getPort("\\Y");
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shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
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}
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else if (shiftx->type == "$mux") {
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l_wire = shiftx->getPort("\\S");
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q_wire = shiftx->getPort("\\Y");
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shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
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}
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else log_abort();
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newcell->setPort("\\Q", q_wire);
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newcell->setPort("\\L", l_wire);
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return false;
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}
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};
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@ -549,7 +509,7 @@ struct ShregmapWorker
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first_cell->setPort(q_port, last_cell->getPort(q_port));
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first_cell->setParam("\\DEPTH", depth);
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if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps_dict))
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if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
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remove_cells.insert(first_cell);
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for (int i = 1; i < depth; i++)
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