From de37070c28c08e1d7a5e18f8c65e4837f51c9e40 Mon Sep 17 00:00:00 2001
From: Gus Smith <guscomps@gmail.com>
Date: Wed, 22 Jun 2022 10:57:46 -0700
Subject: [PATCH 1/2] Support param. default values in JSON FE and SV BE

---
 backends/verilog/verilog_backend.cc | 11 +++++++++++
 frontends/json/jsonparse.cc         |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index aa1d4558c..28cbb4f4d 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -395,6 +395,14 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 	}
 }
 
+void dump_parameter(std::ostream &f, std::string indent, RTLIL::IdString id_string, RTLIL::Const parameter)
+{
+	f << stringf("%sparameter %s", indent.c_str(), id(id_string).c_str());
+	f << stringf(" = ");
+	dump_const(f, parameter);
+	f << stringf(";\n");
+}
+
 void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 {
 	dump_attributes(f, indent, wire->attributes, '\n', /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name));
@@ -2084,6 +2092,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		f << indent + "  " << "reg " << id(initial_id) << " = 0;\n";
 	}
 
+	for (auto p : module->parameter_default_values)
+		dump_parameter(f, indent + "  ", p.first, p.second);
+
 	for (auto w : module->wires())
 		dump_wire(f, indent + "  ", w);
 
diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc
index 1aab81015..96c2d3d77 100644
--- a/frontends/json/jsonparse.cc
+++ b/frontends/json/jsonparse.cc
@@ -302,6 +302,9 @@ void json_import(Design *design, string &modname, JsonNode *node)
 	if (node->data_dict.count("attributes"))
 		json_parse_attr_param(module->attributes, node->data_dict.at("attributes"));
 
+	if (node->data_dict.count("parameter_default_values"))
+		json_parse_attr_param(module->parameter_default_values, node->data_dict.at("parameter_default_values"));
+
 	dict<int, SigBit> signal_bits;
 
 	if (node->data_dict.count("ports"))

From 0275f979c8c2e136b1bed847fd1bc49f3e122a03 Mon Sep 17 00:00:00 2001
From: Gus Smith <guscomps@gmail.com>
Date: Wed, 22 Jun 2022 11:01:43 -0700
Subject: [PATCH 2/2] Support using IDs as const values

---
 backends/verilog/verilog_backend.cc | 5 +++++
 kernel/rtlil.h                      | 3 ++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 28cbb4f4d..52871b881 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -188,6 +188,11 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 
 void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool escape_comment = false)
 {
+	if (data.flags & RTLIL::CONST_FLAG_ID) {
+		f << stringf("%s", data.decode_string().c_str());
+		return;
+	}
+
 	bool set_signed = (data.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 	if (width < 0)
 		width = data.bits.size() - offset;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7a0b6b9c7..d34e63973 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -50,7 +50,8 @@ namespace RTLIL
 		CONST_FLAG_NONE   = 0,
 		CONST_FLAG_STRING = 1,
 		CONST_FLAG_SIGNED = 2,  // only used for parameters
-		CONST_FLAG_REAL   = 4   // only used for parameters
+		CONST_FLAG_REAL   = 4,  // only used for parameters
+		CONST_FLAG_ID     = 5
 	};
 
 	struct Const;