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Merge pull request #4163 from QuantamHD/fix_write_verilog

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write_verilog: Making sure BUF cells are converted to expressions.
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Martin Povišer 2024-01-30 10:58:42 +01:00 committed by GitHub
parent b572e1af9f 3076875fff
commit 3537976477
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1 changed files with 9 additions and 0 deletions
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9
backends/verilog/verilog_backend.cc
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@ -1053,6 +1053,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(";\n"); f << stringf(";\n");
return true; return true;
} }
if (cell->type == ID($_BUF_)) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(";\n");
return true;
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());