From 0deaccbaae436bc94ad5b2913fa39a9368c09ace Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 8 Apr 2019 16:46:33 -0700 Subject: [PATCH 1/7] Fix a few typos --- passes/pmgen/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 223b43059..7a46558b1 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -83,8 +83,8 @@ They are declared like state variables, just using the `udata` statement: udata min_data_width max_data_width udata data_port_name -They are atomatically initialzed to the default constructed value of their type -when ther pattern matcher object is constructed. +They are automatically initialized to the default constructed value of their type +when the pattern matcher object is constructed. Embedded C++ code ----------------- @@ -158,7 +158,7 @@ Finally, `filter ` narrows down the remaining list of cells. For performance reasons `filter` statements should only be used for things that can't be done using `select` and `index`. -The `optional` statement marks optional matches. I.e. the matcher will also +The `optional` statement marks optional matches. That is, the matcher will also explore the case where `mul` is set to `nullptr`. Without the `optional` statement a match may only be assigned nullptr when one of the `if` expressions evaluates to `false`. From adc6efb58468a7e2f85f756d4a9d4686ad0a8c45 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 12:34:51 -0700 Subject: [PATCH 2/7] Recognise default entry in case even if all cases covered (#931) --- passes/proc/proc_rmdead.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 7c334e661..d2f8d9ead 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); + bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; From 7685469ee2f7bc038c4fd6fe98f93eb08d6fac7c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 15:03:40 -0700 Subject: [PATCH 3/7] Add default entry to testcase --- tests/various/muxcover.ys | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys index 7ac460f13..594e62af6 100644 --- a/tests/various/muxcover.ys +++ b/tests/various/muxcover.ys @@ -8,12 +8,13 @@ read_verilog -formal < Date: Thu, 11 Apr 2019 15:09:13 -0700 Subject: [PATCH 4/7] Spelling fixes --- passes/techmap/pmuxtree.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index b7a22dc3b..6a923f481 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -71,9 +71,9 @@ struct PmuxtreePass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" pmuxtree [options] [selection]\n"); + log(" pmuxtree [selection]\n"); log("\n"); - log("This pass transforms $pmux cells to a trees of $mux cells.\n"); + log("This pass transforms $pmux cells to trees of $mux cells.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE From e8c26f2839611f5b52c29f711670888b02066064 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 15:52:04 -0700 Subject: [PATCH 5/7] WIP --- passes/techmap/Makefile.inc | 1 + passes/techmap/pmux2shiftx.cc | 88 +++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 passes/techmap/pmux2shiftx.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index cf9e198ad..81df499da 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -37,6 +37,7 @@ OBJS += passes/techmap/attrmap.o OBJS += passes/techmap/zinit.o OBJS += passes/techmap/dff2dffs.o OBJS += passes/techmap/flowmap.o +OBJS += passes/techmap/pmux2shiftx.o endif GENFILES += passes/techmap/techmap.inc diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc new file mode 100644 index 000000000..6569f995f --- /dev/null +++ b/passes/techmap/pmux2shiftx.cc @@ -0,0 +1,88 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct Pmux2ShiftxPass : public Pass { + Pmux2ShiftxPass() : Pass("pmux2shiftx", "transform $pmux cells to $shiftx cells") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" pmux2shiftx [selection]\n"); + log("\n"); + log("This pass transforms $pmux cells to $shiftx cells.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing PMUX2SHIFTX pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + for (auto cell : module->selected_cells()) + { + if (cell->type != "$pmux") + continue; + + // Create a new encoder, out of a $pmux, that takes + // the existing pmux's 'S' input and transforms it + // back into a binary value + const int s_width = cell->getParam("\\S_WIDTH").as_int(); + const int width = cell->getParam("\\WIDTH").as_int(); + const int clog2width = ceil(log2(s_width)); + RTLIL::SigSpec shiftx_a; + RTLIL::SigSpec pmux_a; + RTLIL::SigSpec pmux_b; + RTLIL::SigSpec b_port = cell->getPort("\\B"); + if (!cell->getPort("\\A").is_fully_undef()) { + pmux_a = RTLIL::Const(RTLIL::S0, clog2width); + shiftx_a.append(cell->getPort("\\A")); + for (int i = s_width; i > 0; i--) { + shiftx_a.append(b_port.extract((i-1)*width, width)); + pmux_b.append(RTLIL::Const(i, clog2width)); + } + + } + else { + pmux_a = RTLIL::Const(RTLIL::Sx, clog2width); + for (int i = s_width-1; i >= 0; i--) { + shiftx_a.append(b_port.extract(i*width, width)); + pmux_b.append(RTLIL::Const(i, clog2width)); + } + } + RTLIL::SigSpec pmux_y = module->addWire(NEW_ID, clog2width); + RTLIL::SigSpec shiftx_s = module->addWire(NEW_ID, 1 << clog2width); + module->addPmux(NEW_ID, pmux_a, pmux_b, cell->getPort("\\S"), pmux_y); + module->addShiftx(NEW_ID, shiftx_a, pmux_y, cell->getPort("\\Y")); + module->remove(cell); + } + } +} Pmux2ShiftxPass; + +PRIVATE_NAMESPACE_END From b1f1db2fcf0e27fbd9cb7b94ab5c9d8879ad9694 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 16:17:09 -0700 Subject: [PATCH 6/7] Fixes --- passes/techmap/pmux2shiftx.cc | 38 ++++++++++++++++------------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc index 6569f995f..9b05f8f6d 100644 --- a/passes/techmap/pmux2shiftx.cc +++ b/passes/techmap/pmux2shiftx.cc @@ -53,32 +53,28 @@ struct Pmux2ShiftxPass : public Pass { // Create a new encoder, out of a $pmux, that takes // the existing pmux's 'S' input and transforms it // back into a binary value - const int s_width = cell->getParam("\\S_WIDTH").as_int(); + RTLIL::SigSpec shiftx_a; + RTLIL::SigSpec pmux_s; + + int s_width = cell->getParam("\\S_WIDTH").as_int(); + if (!cell->getPort("\\A").is_fully_undef()) { + ++s_width; + shiftx_a.append(cell->getPort("\\A")); + pmux_s.append(module->Not(NEW_ID, module->ReduceOr(NEW_ID, cell->getPort("\\S")))); + } const int width = cell->getParam("\\WIDTH").as_int(); const int clog2width = ceil(log2(s_width)); - RTLIL::SigSpec shiftx_a; - RTLIL::SigSpec pmux_a; - RTLIL::SigSpec pmux_b; - RTLIL::SigSpec b_port = cell->getPort("\\B"); - if (!cell->getPort("\\A").is_fully_undef()) { - pmux_a = RTLIL::Const(RTLIL::S0, clog2width); - shiftx_a.append(cell->getPort("\\A")); - for (int i = s_width; i > 0; i--) { - shiftx_a.append(b_port.extract((i-1)*width, width)); - pmux_b.append(RTLIL::Const(i, clog2width)); - } - } - else { - pmux_a = RTLIL::Const(RTLIL::Sx, clog2width); - for (int i = s_width-1; i >= 0; i--) { - shiftx_a.append(b_port.extract(i*width, width)); - pmux_b.append(RTLIL::Const(i, clog2width)); - } - } + RTLIL::SigSpec pmux_b; + pmux_b.append(RTLIL::Const(0, clog2width)); + for (int i = s_width-1; i > 0; i--) + pmux_b.append(RTLIL::Const(i, clog2width)); + shiftx_a.append(cell->getPort("\\B")); + pmux_s.append(cell->getPort("\\S")); + RTLIL::SigSpec pmux_y = module->addWire(NEW_ID, clog2width); RTLIL::SigSpec shiftx_s = module->addWire(NEW_ID, 1 << clog2width); - module->addPmux(NEW_ID, pmux_a, pmux_b, cell->getPort("\\S"), pmux_y); + module->addPmux(NEW_ID, RTLIL::Const(RTLIL::Sx, clog2width), pmux_b, pmux_s, pmux_y); module->addShiftx(NEW_ID, shiftx_a, pmux_y, cell->getPort("\\Y")); module->remove(cell); } From b15b410b41cca3a79bfcfc9c91f665815f31ab5b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 16:18:01 -0700 Subject: [PATCH 7/7] Remove unused --- passes/techmap/pmux2shiftx.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/techmap/pmux2shiftx.cc b/passes/techmap/pmux2shiftx.cc index 9b05f8f6d..08cb06d5f 100644 --- a/passes/techmap/pmux2shiftx.cc +++ b/passes/techmap/pmux2shiftx.cc @@ -73,7 +73,6 @@ struct Pmux2ShiftxPass : public Pass { pmux_s.append(cell->getPort("\\S")); RTLIL::SigSpec pmux_y = module->addWire(NEW_ID, clog2width); - RTLIL::SigSpec shiftx_s = module->addWire(NEW_ID, 1 << clog2width); module->addPmux(NEW_ID, RTLIL::Const(RTLIL::Sx, clog2width), pmux_b, pmux_s, pmux_y); module->addShiftx(NEW_ID, shiftx_a, pmux_y, cell->getPort("\\Y")); module->remove(cell);