mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-04 05:11:22 +00:00
Code Activity

Fixed memory_bram for ROMs in BRAMs with write-enable inputs

Browse source
This commit is contained in:
Clifford Wolf 2015-09-24 11:37:15 +02:00
parent 1b8cb9940e
commit 3501f8e364
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/memory/memory_bram.cc
View file

@ -433,7 +433,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
SigSpec rd_data = cell->getPort("\\RD_DATA"); SigSpec rd_data = cell->getPort("\\RD_DATA");
SigSpec rd_addr = cell->getPort("\\RD_ADDR"); SigSpec rd_addr = cell->getPort("\\RD_ADDR");
if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0) if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0)
{ {
int bucket_size = bram.dbits / portinfos.at(match.shuffle_enable - 'A').enable; int bucket_size = bram.dbits / portinfos.at(match.shuffle_enable - 'A').enable;
log(" Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size); log(" Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size);