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Fixes and add comments for open FIXME items

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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2021-10-08 17:24:45 +02:00
parent 1602a03864
commit 34f1df8435
1 changed files with 34 additions and 1 deletions
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35
frontends/verific/verific.cc
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@ -410,13 +410,23 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
return true; return true;
} }
if (inst->Type() == PRIM_DLATCHRS)
{
if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
else
module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
return true;
}
if (inst->Type() == PRIM_DFF) if (inst->Type() == PRIM_DFF)
{ {
VerificClocking clocking(this, inst->GetClock()); VerificClocking clocking(this, inst->GetClock());
log_assert(clocking.disable_sig == State::S0); log_assert(clocking.disable_sig == State::S0);
log_assert(clocking.body_net == nullptr); log_assert(clocking.body_net == nullptr);
if (inst->GetAsyncVal()->IsGnd()) if (inst->GetAsyncCond()->IsGnd())
clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
else else
clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()), clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()),
@ -424,6 +434,8 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
return true; return true;
} }
// FIXME: PRIM_DLATCH
return false; return false;
} }
@ -534,6 +546,23 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true; return true;
} }
if (inst->Type() == PRIM_DFF)
{
VerificClocking clocking(this, inst->GetClock());
log_assert(clocking.disable_sig == State::S0);
log_assert(clocking.body_net == nullptr);
if (inst->GetAsyncCond()->IsGnd())
cell = clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
else
cell = clocking.addAldff(inst_name, net_map_at(inst->GetAsyncCond()), net_map_at(inst->GetAsyncVal()),
net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
import_attributes(cell->attributes, inst);
return true;
}
// FIXME: PRIM_DLATCH
#define IN operatorInput(inst) #define IN operatorInput(inst)
#define IN1 operatorInput1(inst) #define IN1 operatorInput1(inst)
#define IN2 operatorInput2(inst) #define IN2 operatorInput2(inst)
@ -806,6 +835,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true; return true;
} }
// FIXME: OPER_WIDE_DLATCHSR
if (inst->Type() == OPER_WIDE_DFF) if (inst->Type() == OPER_WIDE_DFF)
{ {
VerificClocking clocking(this, inst->GetClock()); VerificClocking clocking(this, inst->GetClock());
@ -834,6 +865,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true; return true;
} }
// FIXME: OPER_WIDE_DLATCH
#undef IN #undef IN
#undef IN1 #undef IN1
#undef IN2 #undef IN2