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peepopt: avoid shift-amount underflow
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@ -66,7 +66,8 @@ match add
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define <bool> offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A))
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define <bool> offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A))
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// checking some value boundaries as well:
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// checking some value boundaries as well:
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// data[...-c +:W1] is fine for +/-var (pad at LSB, all data still accessible)
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// data[...-c +:W1] is fine for any signed var (pad at LSB, all data still accessible)
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// unsigned shift may underflow (eg var-3 with var<3) -> cannot be converted
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// data[...+c +:W1] is only fine for +var(add) and var unsigned
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// data[...+c +:W1] is only fine for +var(add) and var unsigned
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// (+c cuts lower C bits, making them inaccessible, a signed var could try to access them)
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// (+c cuts lower C bits, making them inaccessible, a signed var could try to access them)
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// either its an add or the variable port is A (it must be positive)
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// either its an add or the variable port is A (it must be positive)
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@ -74,6 +75,8 @@ match add
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// -> data[var+c +:W1] (with var signed) is illegal
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// -> data[var+c +:W1] (with var signed) is illegal
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filter !(!offset_negative && varport_signed)
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filter !(!offset_negative && varport_signed)
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// -> data >> (var-c) (with var unsigned) is illegal
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filter !(offset_negative && !varport_signed)
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// state-variables are assigned at the end only:
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// state-variables are assigned at the end only:
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// shift the log2scale offset in-front of add to get true value: (var+c)<<N -> (var<<N)+(c<<N)
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// shift the log2scale offset in-front of add to get true value: (var+c)<<N -> (var<<N)+(c<<N)
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15
tests/opt/bug4413.ys
Normal file
15
tests/opt/bug4413.ys
Normal file
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@ -0,0 +1,15 @@
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read_verilog <<EOT
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module top(
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input wire shift,
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input wire [4:0] data,
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output wire out
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);
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wire [1:0] shift2 = shift - 1'b1;
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assign out = data >> shift2;
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endmodule
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EOT
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equiv_opt -assert peepopt
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