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presentation progress

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Clifford Wolf 2014-01-29 15:56:58 +01:00
parent cbe77bf844
commit 34b39ec28a
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manual/PRESENTATION_Intro.tex
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@ -374,3 +374,35 @@ clean
\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{More Yosys Commands}
\begin{frame}{\subsecname{} -- TBD}
TBD
\end{frame}
\subsection{More Verilog Examples}
\begin{frame}{\subsecname{} -- TBD}
TBD
\end{frame}
\subsection{Verification}
\begin{frame}{\subsecname{} -- VlogHammer}
TBD
\end{frame}
\begin{frame}{\subsecname{} -- yosys-bigsim}
TBD
\end{frame}
\subsection{Benefits of Open Source HDL Synthesis}
\begin{frame}{\subsecname}
TBD
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%