3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 22:33:41 +00:00

presentation progress

This commit is contained in:
Clifford Wolf 2014-01-29 15:56:58 +01:00
parent cbe77bf844
commit 34b39ec28a
2 changed files with 36 additions and 4 deletions

View file

@ -2,17 +2,17 @@
read_verilog counter.v
hierarchy -check -top counter
show -format pdf -prefix counter_00
show -stretch -format pdf -prefix counter_00
# the high-level stuff
proc; opt; memory; opt; fsm; opt
show -format pdf -prefix counter_01
show -stretch -format pdf -prefix counter_01
# mapping to internal cell library
techmap; splitnets -ports; opt
show -format pdf -prefix counter_02
show -stretch -format pdf -prefix counter_02
# mapping flip-flops to mycells.lib
dfflibmap -liberty mycells.lib
@ -23,4 +23,4 @@ abc -liberty mycells.lib
# cleanup
clean
show -lib mycells.v -format pdf -prefix counter_03
show -stretch -lib mycells.v -format pdf -prefix counter_03