mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-21 18:50:38 +00:00
Code Activity

changes related to some pull request remarks

Browse source
This commit is contained in:
Artur Swiderski 2020-12-09 14:35:01 +01:00
parent dd9c11c035
commit 349fc479cb
3 changed files with 3 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/intel_le/common/quartus_rename.v
View file

@ -58,7 +58,7 @@ assign Q = ~A;
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D, CI, output SO, CO);
module MISTRAL_LE_LUT_ARITH(input A, B, C, D, CI, output SO, CO);
parameter LUT = 16'h0000;
`LCELL #(.lut_mask({LUT}),.sum_lutc_input("cin")) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .cin(CI), .combout(SO), .cout(CO));