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Make liberal use of IdString.in()

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This commit is contained in:
Eddie Hung 2019-08-06 16:18:18 -07:00
parent 43081337fa
commit 3486235338
18 changed files with 45 additions and 51 deletions
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16
passes/techmap/abc.cc
View file

@ -166,7 +166,7 @@ void mark_port(RTLIL::SigSpec sig)
void extract_cell(RTLIL::Cell *cell, bool keepff)
{
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
if (clk_polarity != (cell->type == "$_DFF_P_"))
return;
@ -177,11 +177,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
goto matching_dff;
}
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{
if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"))
if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"))
return;
if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"))
if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"))
return;
if (clk_sig != assign_map(cell->getPort("\\C")))
return;
@ -1824,15 +1824,15 @@ struct AbcPass : public Pass {
}
}
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_"))
{
bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else

8
passes/techmap/abc9.cc
View file

@ -1137,15 +1137,15 @@ struct Abc9Pass : public Pass {
}
}
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
}
else
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{
bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
}
else

2
passes/techmap/aigmap.cc
View file

@ -66,7 +66,7 @@ struct AigmapPass : public Pass {
{
Aig aig(cell);
if (cell->type == "$_AND_" || cell->type == "$_NOT_")
if (cell->type.in("$_AND_", "$_NOT_"))
aig.name.clear();
if (nand_mode && cell->type == "$_NAND_")

2
passes/techmap/deminout.cc
View file

@ -85,7 +85,7 @@ struct DeminoutPass : public Pass {
if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf"))
{
bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf");
bool tribuf = cell->type.in("$_TBUF_", "$tribuf");
if (!tribuf) {
for (auto &c : cell->connections()) {

4
passes/techmap/dff2dffe.cc
View file

@ -52,13 +52,13 @@ struct Dff2dffeWorker
}
for (auto cell : module->cells()) {
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") {
if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
}
if (direct_dict.empty()) {
if (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_"))
dff_cells.push_back(cell);
} else {
if (direct_dict.count(cell->type))

2
passes/techmap/simplemap.cc
View file

@ -245,7 +245,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
bool is_ne = cell->type == "$ne" || cell->type == "$nex";
bool is_ne = cell->type.in("$ne", "$nex");
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);