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Make liberal use of IdString.in()
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parent
43081337fa
commit
3486235338
18 changed files with 45 additions and 51 deletions
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@ -94,8 +94,8 @@ struct OptMergeWorker
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const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
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dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
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if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
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cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
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if (cell->type.in("$and", "$or", "$xor", "$xnor", "$add", "$mul",
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"$logic_and", "$logic_or", "$_AND_", "$_OR_", "$_XOR_")) {
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alt_conn = *conn;
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if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
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alt_conn["\\A"] = conn->at("\\B");
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@ -103,13 +103,13 @@ struct OptMergeWorker
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}
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conn = &alt_conn;
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} else
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if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") {
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if (cell->type.in("$reduce_xor", "$reduce_xnor")) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at("\\A"));
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alt_conn.at("\\A").sort();
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conn = &alt_conn;
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} else
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if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") {
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if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at("\\A"));
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alt_conn.at("\\A").sort_and_unify();
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