mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

xilinx: Fix srl regression.

Browse source 
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9.  Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
This commit is contained in:
Marcelina Kościelnicka 2020-07-12 17:54:07 +02:00
parent b33744b03a
commit 347dd01c2f
2 changed files with 43 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/xilinx/synth_xilinx.cc
View file

@ -652,13 +652,13 @@ struct SynthXilinxPass : public ScriptPass
}
run("clean");
if (help_mode || !abc9)
run("techmap -map +/xilinx/ff_map.v", "(only if not '-abc9')");
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
if (!nosrl || help_mode)
run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
if (help_mode || !abc9)
techmap_args += stringf(" -map +/xilinx/ff_map.v");
techmap_args += " -D LUT_WIDTH=" + lut_size_s;
run("techmap " + techmap_args);
if (help_mode)