diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 39c6cc17a..7e7318153 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1477,9 +1477,13 @@ struct SelectPass : public Pass {
 					log_warning("Ignoring line without slash in 'select -read': %s\n", line);
 					continue;
 				}
-				IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos));
-				IdString obj_name = RTLIL::escape_id(line.substr(slash_pos+1));
-				sel.selected_members[design->twines.add(std::string{mod_name.str()})].insert(design->twines.add(std::string{obj_name.str()}));
+				std::string mod_name = RTLIL::escape_id(line.substr(0, slash_pos));
+				std::string obj_name = RTLIL::escape_id(line.substr(slash_pos+1));
+				TwineRef mod_ref = search.find(mod_name);
+				TwineRef obj_ref = search.find(obj_name);
+				if (mod_ref == Twine::Null || obj_ref == Twine::Null)
+					continue;
+				sel.selected_members[mod_ref].insert(obj_ref);
 			}
 
 			select_filter_active_mod(design, sel);
diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
index f5f981fe9..471a1f271 100644
--- a/passes/techmap/cellmatch.cc
+++ b/passes/techmap/cellmatch.cc
@@ -274,27 +274,27 @@ struct CellmatchPass : Pass {
 							log("Module %s matches %s\n", m, target.module);
 							// Add target.module to map_design ("$cellmatch")
 							// as a techmap rule to match m and replace it with target.module
-							Module *map = map_design->addModule(map_design->twines.add(std::string{stringf("\\_60_%s_%s", m, target.module)}));
-							Cell *cell = map->addCell(TW::_TECHMAP_REPLACE_, Twine{target.module->name.str()});
+							Module *map = map_design->addModule(map_design->twines.add(stringf("\\_60_%s_%s", m, target.module)));
+							Cell *cell = map->addCell(TW::_TECHMAP_REPLACE_, map_design->twines.copy_from(target.module->design->twines, target.module->name));
 
 							map->attributes[ID(techmap_celltype)] = m->name.str();
 
 							for (int i = 0; i < outputs.size(); i++) {
 								log_assert(outputs[i].is_wire());
-								Wire *w = map->addWire(Twine{outputs[i].wire->name.str()}, 1);
+								Wire *w = map->addWire(map_design->twines.copy_from(m->design->twines, outputs[i].wire->name.ref()), 1);
 								w->port_id = outputs[i].wire->port_id;
 								w->port_output = true;
 								log_assert(target_outputs[output_map[i]].is_wire());
-								cell->setPort(map_design->twines.add(std::string{target_outputs[output_map[i]].wire->name.str()}), w);
+								cell->setPort(map_design->twines.copy_from(target.module->design->twines, target_outputs[output_map[i]].wire->name.ref()), w);
 							}
 
 							for (int i = 0; i < inputs.size(); i++) {
 								log_assert(inputs[i].is_wire());
-								Wire *w = map->addWire(Twine{inputs[i].wire->name.str()}, 1);
+								Wire *w = map->addWire(map_design->twines.copy_from(m->design->twines, inputs[i].wire->name.ref()), 1);
 								w->port_id = inputs[i].wire->port_id;
 								w->port_input = true;
 								log_assert(target_inputs[input_map[i]].is_wire());
-								cell->setPort(map_design->twines.add(std::string{target_inputs[input_map[i]].wire->name.str()}), w);
+								cell->setPort(map_design->twines.copy_from(target.module->design->twines, target_inputs[input_map[i]].wire->name.ref()), w);
 							}
 
 							map->fixup_ports();