twine

tests/arch/gatemate/fsm.ys

@@ -35,8 +35,8 @@ cd fsm # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_BUFG
 select -assert-count 6 t:CC_DFF
 select -assert-max 2 t:CC_LUT1
-select -assert-count 1 t:CC_LUT2
-select -assert-max 15 t:CC_L2T4
+select -assert-count 2 t:CC_LUT2
+select -assert-max 14 t:CC_L2T4
 select -assert-max 5 t:CC_L2T5
 select -assert-max 1 t:CC_MX2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 t:CC_MX2 %% t:* %D

tests/rtlil/no-pipe-leaf.sh

@@ -0,0 +1,49 @@
+set -euo pipefail
+
+mkdir -p temp
+
+# Synthesize a tiny design through paths that previously round-tripped
+# src through get_src_attribute() → set_src_attribute() and broke the
+# flat-leaf invariant: opt_merge -share_all produces a Concat src on the
+# surviving cell, then opt_dff / FfData emit re-emits the cell. Before
+# the adopt_src_from refactor every pipe-joined flatten was re-interned
+# as a single pipe-containing Leaf — now those paths transfer the id
+# verbatim and no Leaf ever contains '|'.
+cat > temp/pipe.v <<'EOF'
+module top(input clk, input [7:0] a, b, c, d, output reg [7:0] x, y);
+  always @(posedge clk) begin
+    x <= a + b;
+    y <= c + d;
+  end
+endmodule
+EOF
+
+${YOSYS} -p "read_verilog temp/pipe.v; hierarchy -top top; proc; opt; opt_merge -share_all; alumacc; opt_dff; dump_twines" \
+    > temp/pipe-dump.txt 2>&1
+
+if grep -E '^\s*@[0-9]+ leaf rc=[0-9]+ ' temp/pipe-dump.txt | grep -q '|'; then
+    echo "FAIL: dump_twines produced a leaf containing '|':" >&2
+    grep -E '^\s*@[0-9]+ leaf rc=[0-9]+ ' temp/pipe-dump.txt | grep '|' >&2
+    exit 1
+fi
+
+# A second pattern that exercises the memory-mapping code path
+# (Mem::extract_rdff stash + FfData::emit).
+cat > temp/mem.v <<'EOF'
+module mem(input clk, input we, input [3:0] addr, input [7:0] din, output reg [7:0] dout);
+  reg [7:0] m [0:15];
+  always @(posedge clk) begin
+    if (we) m[addr] <= din;
+    dout <= m[addr];
+  end
+endmodule
+EOF
+
+${YOSYS} -p "read_verilog temp/mem.v; hierarchy -top mem; proc; opt; memory_map; opt_dff; dump_twines" \
+    > temp/mem-dump.txt 2>&1
+
+if grep -E '^\s*@[0-9]+ leaf rc=[0-9]+ ' temp/mem-dump.txt | grep -q '|'; then
+    echo "FAIL: dump_twines (memory_map path) produced a leaf containing '|':" >&2
+    grep -E '^\s*@[0-9]+ leaf rc=[0-9]+ ' temp/mem-dump.txt | grep '|' >&2
+    exit 1
+fi

tests/rtlil/roundtrip-suffix.sh

@@ -0,0 +1,32 @@
+set -euo pipefail
+
+mkdir -p temp
+
+# Read a hand-crafted RTLIL file with Suffix twine nodes, write it back,
+# and verify byte-for-byte roundtrip — exercises the Suffix parser path,
+# the Suffix backend emitter, and Design::clone_into across design -push
+# (which must preserve Suffix tree topology verbatim).
+${YOSYS} -p "read_rtlil suffix-twines.il; write_rtlil temp/suffix-twines-write.il"
+tail -n +2 temp/suffix-twines-write.il > temp/suffix-twines-write-nogen.il
+diff suffix-twines.il temp/suffix-twines-write-nogen.il
+
+${YOSYS} -p "read_rtlil suffix-twines.il; design -push; design -pop; write_rtlil temp/suffix-twines-push.il"
+tail -n +2 temp/suffix-twines-push.il > temp/suffix-twines-push-nogen.il
+diff suffix-twines.il temp/suffix-twines-push-nogen.il
+
+# Multi-level Suffix chain — verifies that Suffix-with-Suffix-parent
+# survives read/write and a design -push/-pop verbatim cycle.
+${YOSYS} -p "read_rtlil suffix-chain.il; design -push; design -pop; write_rtlil temp/suffix-chain-push.il"
+tail -n +2 temp/suffix-chain-push.il > temp/suffix-chain-push-nogen.il
+diff suffix-chain.il temp/suffix-chain-push-nogen.il
+
+# Verify that gc preserves the Suffix tree (number of nodes and the
+# materialized leaf strings on each cell src), even if the rebuilt pool
+# is renumbered by hash-set iteration order.
+${YOSYS} -p "read_rtlil suffix-chain.il; gc_twines; write_rtlil -resolve-src temp/suffix-chain-gc-resolved.il"
+grep '\\src' temp/suffix-chain-gc-resolved.il | sort > temp/suffix-chain-gc-resolved.srcs
+cat > temp/suffix-chain-expected.srcs <<EOF
+  attribute \\src "/home/emil/repo/foo/bar.v:10.1-10.5"
+  attribute \\src "/home/emil/repo/foo/bar.v:11.1-11.5"
+EOF
+diff temp/suffix-chain-expected.srcs temp/suffix-chain-gc-resolved.srcs

tests/rtlil/suffix-chain.il

@@ -0,0 +1,15 @@
+autoidx 1
+twines
+  leaf 0 "/home/emil/repo/"
+  suffix 1 0 "foo/"
+  suffix 2 1 "bar.v"
+  suffix 3 2 ":10.1-10.5"
+  suffix 4 2 ":11.1-11.5"
+end
+module \chain
+  attribute \src "@3"
+  wire input 1 \a
+  attribute \src "@4"
+  wire output 2 \b
+  connect \b \a
+end

tests/rtlil/suffix-twines.il

@@ -0,0 +1,15 @@
+autoidx 1
+twines
+  leaf 0 "everything.v"
+  suffix 1 0 ":1.1-1.10"
+  suffix 2 0 ":2.5-2.8"
+  concat 3 1 2
+end
+attribute \src "@3"
+module \tiny
+  attribute \src "@1"
+  wire input 1 \a
+  attribute \src "@2"
+  wire output 2 \b
+  connect \b \a
+end

tests/various/json_escape_chars.ys

@@ -10,5 +10,5 @@ read_json temp/test_escapes.json
 write_json temp/test_escapes.json
 design -reset
 read_json temp/test_escapes.json
-write_rtlil temp/test_escapes.json.il
+write_rtlil -resolve-src temp/test_escapes.json.il
 ! grep -F 'attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033"' temp/test_escapes.json.il