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twine

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This commit is contained in:
Emil J. Tywoniak 2026-06-05 12:04:19 +02:00
parent 3d27e83d0f
commit 3424c00cd0
63 changed files with 2635 additions and 503 deletions
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4
passes/techmap/abc.cc
View file

@ -1551,8 +1551,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
for (auto w : mapped_mod->wires()) {
RTLIL::Wire *orig_wire = nullptr;
RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
if (orig_wire != nullptr && orig_wire->attributes.count(ID::src))
wire->attributes[ID::src] = orig_wire->attributes[ID::src];
if (orig_wire != nullptr && orig_wire->src_id() != Twine::Null && module->design)
wire->set_src_id(&module->design->src_twines, orig_wire->src_id());
if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
design->select(module, wire);
}

14
passes/techmap/alumacc.cc
View file

@ -71,7 +71,7 @@ struct AlumaccWorker
get_lt(is_signed);
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_slt, cached_eq);
cached_sgt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
cached_sgt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->src_ref());
}
return cached_sgt;
@ -80,7 +80,7 @@ struct AlumaccWorker
get_lt(is_signed);
get_eq();
SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->src_ref());
}
return cached_gt;
@ -89,13 +89,13 @@ struct AlumaccWorker
RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->src_ref());
return cached_eq;
}
RTLIL::SigSpec get_ne() {
if (GetSize(cached_ne) == 0)
cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->src_ref());
return cached_ne;
}
@ -103,7 +103,7 @@ struct AlumaccWorker
if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort(ID::CO);
log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->src_ref());
}
return cached_cf;
}
@ -385,7 +385,7 @@ struct AlumaccWorker
log(" creating $macc cell for %s: %s\n", n->cell, cell);
cell->set_src_attribute(n->cell->get_src_attribute());
cell->adopt_src_from(n->cell);
n->macc.optimize(GetSize(n->y));
n->macc.to_cell(cell);
@ -518,7 +518,7 @@ struct AlumaccWorker
log(": %s\n", n->alu_cell);
if (n->cells.size() > 0)
n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute());
n->alu_cell->adopt_src_from(n->cells[0]);
n->alu_cell->setPort(ID::A, n->a);
n->alu_cell->setPort(ID::B, n->b);

4
passes/techmap/bmuxmap.cc
View file

@ -75,7 +75,7 @@ struct BmuxmapPass : public Pass {
module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
}
RTLIL::Cell *pmux = module->addPmux(NEW_ID, new_a, data, new_s, new_data);
pmux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
module->design->merge_src(pmux, cell);
data = new_data;
}
else
@ -88,7 +88,7 @@ struct BmuxmapPass : public Pass {
data.extract(i*2+width, width),
sel[idx],
new_data.extract(i, width));
mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
module->design->merge_src(mux, cell);
}
data = new_data;
}

6
passes/techmap/demuxmap.cc
View file

@ -58,17 +58,17 @@ struct DemuxmapPass : public Pass {
for (int i = 0; i < 1 << GetSize(sel); i++) {
if (width == 1 && data == State::S1) {
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]);
eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
module->design->merge_src(eq_cell, cell);
} else {
Wire *eq = module->addWire(NEW_ID);
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq);
eq_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
module->design->merge_src(eq_cell, cell);
RTLIL::Cell *mux = module->addMux(NEW_ID,
Const(State::S0, width),
data,
eq,
out.extract(i*width, width));
mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
module->design->merge_src(mux, cell);
}
}

2
passes/techmap/extract_counter.cc
View file

@ -532,7 +532,7 @@ void counter_worker(
RTLIL::Wire* port_wire = port.as_wire();
bool force_extract = false;
bool never_extract = false;
string count_reg_src = port_wire->attributes[ID::src].decode_string().c_str();
string count_reg_src = port_wire->get_src_attribute().c_str();
if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end())
{
pool<string> sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT));

2
passes/techmap/flowmap.cc
View file

@ -1416,7 +1416,7 @@ struct FlowmapWorker
for (auto gate_node : lut_gates[node])
{
auto gate_origin = node_origins[gate_node];
lut->add_strpool_attribute(ID::src, gate_origin.cell->get_strpool_attribute(ID::src));
module->design->merge_src(lut, gate_origin.cell);
packed_count++;
}
lut_count++;

7
passes/techmap/simplemap.cc
View file

@ -27,12 +27,9 @@
USING_YOSYS_NAMESPACE
YOSYS_NAMESPACE_BEGIN
static void transfer_attr (Cell* to, const Cell* from, IdString attr) {
if (from->has_attribute(attr))
to->attributes[attr] = from->attributes.at(attr);
}
static void transfer_src (Cell* to, const Cell* from) {
transfer_attr(to, from, ID::src);
if (from->src_id() != Twine::Null && to->module && to->module->design)
to->set_src_id(&to->module->design->src_twines, from->src_id());
}
void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)

23
passes/techmap/techmap.cc
View file

@ -157,7 +157,11 @@ struct TechmapWorker
}
std::string orig_cell_name;
pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
// Cache the source cell's src attribute (a "@N" ref or a legacy
// literal). Each technology-mapped object inherits this via
// design->merge_src, which routes through the twine pool so
// successive merges share substructure.
const RTLIL::Cell *src_cell = cell;
orig_cell_name = cell->name.str();
for (auto tpl_cell : tpl->cells())
@ -172,8 +176,8 @@ struct TechmapWorker
IdString m_name = it.first;
apply_prefix(cell->name, m_name);
RTLIL::Memory *m = module->addMemory(m_name, it.second);
if (m->attributes.count(ID::src))
m->add_strpool_attribute(ID::src, extra_src_attrs);
if (m->has_attribute(ID::src))
design->merge_src(m, src_cell);
memory_renames[it.first] = m->name;
design->select(module, m);
}
@ -217,8 +221,8 @@ struct TechmapWorker
w->attributes.erase(ID::techmap_autopurge);
if (tpl_w->get_bool_attribute(ID::_techmap_special_))
w->attributes.clear();
if (w->attributes.count(ID::src))
w->add_strpool_attribute(ID::src, extra_src_attrs);
if (w->has_attribute(ID::src))
design->merge_src(w, src_cell);
}
design->select(module, w);
@ -377,8 +381,8 @@ struct TechmapWorker
c->setParam(ID::MEMID, Const(memid.c_str()));
}
if (c->attributes.count(ID::src))
c->add_strpool_attribute(ID::src, extra_src_attrs);
if (c->has_attribute(ID::src))
design->merge_src(c, src_cell);
if (techmap_replace_cell) {
for (auto attr : cell->attributes)
@ -514,8 +518,9 @@ struct TechmapWorker
{
extmapper_module = extmapper_design->addModule(m_name);
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
extmapper_cell->set_src_attribute(cell->get_src_attribute());
// addCell(name, cell) already migrated src across
// designs via copy_src_into — no need for an
// explicit set_src_attribute round-trip here.
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {

2
passes/techmap/tribuf.cc
View file

@ -145,7 +145,7 @@ struct TribufWorker {
std::string name = stringf("$tribuf_conflict$%s", cell->name.unescape());
auto assert_cell = module->addAssert(name, module->Not(NEW_ID, conflict), SigSpec(true));
assert_cell->set_src_attribute(cell->get_src_attribute());
assert_cell->adopt_src_from(cell);
assert_cell->set_bool_attribute(ID::keep);
module->design->scratchpad_set_bool("tribuf.added_something", true);