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https://github.com/YosysHQ/yosys
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Add symfpu -classify
Add description text for standard `symfpu` signature.
This commit is contained in:
Krystine Sherwin
parent
826d1d91cd
commit
341cd563bd
1 changed files with 108 additions and 70 deletions
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@ -29,6 +29,7 @@
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#include "libs/symfpu/core/packing.h"
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#include "libs/symfpu/core/sqrt.h"
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#include "libs/symfpu/core/unpackedFloat.h"
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#include "libs/symfpu/core/classify.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -391,9 +392,17 @@ struct SymFpuPass : public Pass {
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auto content_root = help->get_root();
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content_root->usage("symfpu [options]");
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content_root->paragraph("TODO");
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content_root->usage("symfpu [size] [-op <OP>] [-rm <RM>]");
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content_root->paragraph(
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"Generates netlist for given floating point operation with floating point inputs"
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"a, b, c, floating point output o, 5-bit input rm (rounding mode), and "
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"5 single-bit outputs NV (invalid operation), DZ (divide by zero), OF (overflow), "
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"UF (underflow), and NX (inexact)."
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);
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content_root->paragraph(
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"Operations use single precision float unless [size] options are provided:"
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);
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content_root->option("-eb <N>", "use <N> bits for exponent; default=8");
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content_root->option("-sb <N>", "use <N> bits for significand, including hidden bit; default=24");
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@ -425,6 +434,13 @@ struct SymFpuPass : public Pass {
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);
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rm_option->paragraph("Note: when not using DYN mode, the 'rm' input is ignored.");
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content_root->usage("symfpu -classify [size]");
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content_root->paragraph(
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"Generates netlist for floating point classification of input a. Outputs "
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"8 single-bit signals, isNormal, isSubnormal, isZero, isInfinite, isNaN, "
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"isPositive, isNegative, and isFinite."
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);
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return true;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -433,6 +449,7 @@ struct SymFpuPass : public Pass {
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int eb = 8, sb = 24;
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string op = "mul", rounding = "DYN";
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int inputs = 2;
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bool classify = false;
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log_header(design, "Executing SYMFPU pass.\n");
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size_t argidx;
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@ -468,11 +485,22 @@ struct SymFpuPass : public Pass {
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rounding = args[++argidx];
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continue;
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}
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if (args[argidx] == "-classify") {
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classify = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (classify) {
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if (rounding.compare("DYN") != 0)
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log_cmd_error("symfpu -classify does not support rounding modes.\n");
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if (op.compare("mul") != 0)
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log_cmd_error("symfpu -classify does not support operator selection.\n");
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}
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rm rounding_mode;
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if (rounding.compare("RNE") == 0)
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rounding_mode = rtlil_traits::RNE();
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@ -496,80 +524,90 @@ struct SymFpuPass : public Pass {
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symfpu_mod = mod;
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auto a_bv = input_ubv(ID(a), eb+sb);
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auto b_bv = input_ubv(ID(b), eb+sb);
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auto c_bv = input_ubv(ID(c), eb+sb);
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uf a = symfpu::unpack<rtlil_traits>(format, a_bv);
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uf b = symfpu::unpack<rtlil_traits>(format, b_bv);
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uf c = symfpu::unpack<rtlil_traits>(format, c_bv);
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auto rm_wire = symfpu_mod->addWire(ID(rm), 5);
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rm_wire->port_input = true;
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SigSpec rm_sig(rm_wire);
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prop rm_RNE(rm_sig[0]);
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prop rm_RNA(rm_sig[1]);
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prop rm_RTP(rm_sig[2]);
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prop rm_RTN(rm_sig[3]);
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prop rm_RTZ(rm_sig[4]);
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if (classify) {
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output_prop(ID(isNormal), symfpu::isNormal(format, a));
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output_prop(ID(isSubnormal), symfpu::isSubnormal(format, a));
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output_prop(ID(isZero), symfpu::isZero(format, a));
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output_prop(ID(isInfinite), symfpu::isInfinite(format, a));
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output_prop(ID(isNaN), symfpu::isNaN(format, a));
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output_prop(ID(isPositive), symfpu::isPositive(format, a));
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output_prop(ID(isNegative), symfpu::isNegative(format, a));
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output_prop(ID(isFinite), symfpu::isFinite(format, a));
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} else {
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auto b_bv = input_ubv(ID(b), eb+sb);
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auto c_bv = input_ubv(ID(c), eb+sb);
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uf b = symfpu::unpack<rtlil_traits>(format, b_bv);
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uf c = symfpu::unpack<rtlil_traits>(format, c_bv);
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// signaling NaN inputs raise NV
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prop signals_invalid((a.getNaN() && is_sNaN(a_bv, sb))
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|| (b.getNaN() && is_sNaN(b_bv, sb) && inputs >= 2)
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|| (c.getNaN() && is_sNaN(c_bv, sb) && inputs >= 3)
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);
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auto rm_wire = symfpu_mod->addWire(ID(rm), 5);
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rm_wire->port_input = true;
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SigSpec rm_sig(rm_wire);
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prop rm_RNE(rm_sig[0]);
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prop rm_RNA(rm_sig[1]);
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prop rm_RTP(rm_sig[2]);
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prop rm_RTN(rm_sig[3]);
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prop rm_RTZ(rm_sig[4]);
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auto make_op = [&op, &format, &a, &b, &c](rm rounding_mode) {
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if (op.compare("add") == 0)
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return symfpu::add_flagged(format, rounding_mode, a, b, prop(true));
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else if (op.compare("sub") == 0)
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return symfpu::add_flagged(format, rounding_mode, a, b, prop(false));
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else if (op.compare("mul") == 0)
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return symfpu::multiply_flagged(format, rounding_mode, a, b);
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else if (op.compare("div") == 0)
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return symfpu::divide_flagged(format, rounding_mode, a, b);
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else if (op.compare("sqrt") == 0)
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return symfpu::sqrt_flagged(format, rounding_mode, a);
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else if (op.compare("muladd") == 0)
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return symfpu::fma_flagged(format, rounding_mode, a, b, c);
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else if (op.compare("altdiv") == 0)
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return symfpu::falseDivide_flagged(format, rounding_mode, a, b, prop(true));
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else if (op.compare("alt2div") == 0)
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return symfpu::falseDivide_flagged(format, rounding_mode, a, b, prop(false));
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else if (op.compare("altsqrt") == 0)
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return symfpu::falseSqrt_flagged(format, rounding_mode, a);
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else
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log_abort();
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};
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// calling this more than once will fail
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auto output_fpu = [&signals_invalid, &format](const uf_flagged &o_flagged) {
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output_prop(ID(NV), o_flagged.nv || signals_invalid);
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output_prop(ID(DZ), o_flagged.dz);
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output_prop(ID(OF), o_flagged.of);
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output_prop(ID(UF), o_flagged.uf);
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output_prop(ID(NX), o_flagged.nx);
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output_ubv(ID(o), symfpu::pack<rtlil_traits>(format, o_flagged.val));
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};
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if (rounding.compare("DYN") != 0)
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output_fpu(make_op(rounding_mode));
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else {
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auto out_RNE = make_op(rtlil_traits::RNE());
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auto out_RNA = make_op(rtlil_traits::RNA());
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auto out_RTP = make_op(rtlil_traits::RTP());
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auto out_RTN = make_op(rtlil_traits::RTN());
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auto out_RTZ = make_op(rtlil_traits::RTZ());
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output_fpu(
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uf_flagged_ite::iteOp(rm_RNE, out_RNE,
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uf_flagged_ite::iteOp(rm_RNA, out_RNA,
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uf_flagged_ite::iteOp(rm_RTP, out_RTP,
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uf_flagged_ite::iteOp(rm_RTN, out_RTN,
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uf_flagged_ite::iteOp(rm_RTZ, out_RTZ,
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uf_flagged::makeNaN(format, prop(true)))))))
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// signaling NaN inputs raise NV
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prop signals_invalid((a.getNaN() && is_sNaN(a_bv, sb))
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|| (b.getNaN() && is_sNaN(b_bv, sb) && inputs >= 2)
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|| (c.getNaN() && is_sNaN(c_bv, sb) && inputs >= 3)
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);
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auto make_op = [&op, &format, &a, &b, &c](rm rounding_mode) {
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if (op.compare("add") == 0)
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return symfpu::add_flagged(format, rounding_mode, a, b, prop(true));
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else if (op.compare("sub") == 0)
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return symfpu::add_flagged(format, rounding_mode, a, b, prop(false));
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else if (op.compare("mul") == 0)
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return symfpu::multiply_flagged(format, rounding_mode, a, b);
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else if (op.compare("div") == 0)
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return symfpu::divide_flagged(format, rounding_mode, a, b);
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else if (op.compare("sqrt") == 0)
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return symfpu::sqrt_flagged(format, rounding_mode, a);
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else if (op.compare("muladd") == 0)
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return symfpu::fma_flagged(format, rounding_mode, a, b, c);
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else if (op.compare("altdiv") == 0)
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return symfpu::falseDivide_flagged(format, rounding_mode, a, b, prop(true));
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else if (op.compare("alt2div") == 0)
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return symfpu::falseDivide_flagged(format, rounding_mode, a, b, prop(false));
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else if (op.compare("altsqrt") == 0)
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return symfpu::falseSqrt_flagged(format, rounding_mode, a);
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else
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log_abort();
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};
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// calling this more than once will fail
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auto output_fpu = [&signals_invalid, &format](const uf_flagged &o_flagged) {
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output_prop(ID(NV), o_flagged.nv || signals_invalid);
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output_prop(ID(DZ), o_flagged.dz);
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output_prop(ID(OF), o_flagged.of);
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output_prop(ID(UF), o_flagged.uf);
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output_prop(ID(NX), o_flagged.nx);
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output_ubv(ID(o), symfpu::pack<rtlil_traits>(format, o_flagged.val));
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};
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if (rounding.compare("DYN") != 0)
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output_fpu(make_op(rounding_mode));
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else {
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auto out_RNE = make_op(rtlil_traits::RNE());
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auto out_RNA = make_op(rtlil_traits::RNA());
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auto out_RTP = make_op(rtlil_traits::RTP());
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auto out_RTN = make_op(rtlil_traits::RTN());
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auto out_RTZ = make_op(rtlil_traits::RTZ());
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output_fpu(
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uf_flagged_ite::iteOp(rm_RNE, out_RNE,
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uf_flagged_ite::iteOp(rm_RNA, out_RNA,
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uf_flagged_ite::iteOp(rm_RTP, out_RTP,
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uf_flagged_ite::iteOp(rm_RTN, out_RTN,
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uf_flagged_ite::iteOp(rm_RTZ, out_RTZ,
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uf_flagged::makeNaN(format, prop(true)))))))
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);
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}
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}
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symfpu_mod->fixup_ports();
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}
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