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Merge https://github.com/azonenberg/yosys

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Clifford Wolf 2016-04-23 10:33:32 +02:00
commit 34195f281f
1 changed files with 7 additions and 1 deletions
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8
techlibs/greenpak4/cells_sim.v
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@ -235,7 +235,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
reg[15:0] shreg = 0; reg[15:0] shreg = 0;
always @(posedge clk, negedge RSTN) begin always @(posedge clk, negedge nRST) begin
if(!nRST) if(!nRST)
shreg = 0; shreg = 0;
@ -263,6 +263,12 @@ module GP_VDD(output OUT);
assign OUT = 1; assign OUT = 1;
endmodule endmodule
module GP_VREF(input VIN, output reg VOUT);
parameter VIN_DIV = 1;
parameter VREF = 0;
//cannot simulate mixed signal IP
endmodule
module GP_VSS(output OUT); module GP_VSS(output OUT);
assign OUT = 0; assign OUT = 0;
endmodule endmodule