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Merge pull request #5000 from YosysHQ/krys/re_refactor_selections

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N. Engelhardt 2025-04-10 16:06:36 +00:00 • committed by GitHub
commit 3410e10ed5
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45 changed files with 1110 additions and 301 deletions
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14
passes/techmap/abc9.cc
View file

@ -306,9 +306,10 @@ struct Abc9Pass : public ScriptPass
}
run("design -stash $abc9");
run("design -load $abc9_map");
run("proc");
if (help_mode) run("select =*");
else active_design->push_complete_selection();
run("wbflip");
run("techmap -wb -map %$abc9 -map +/techmap.v A:abc9_flop");
run("techmap -autoproc -wb -map %$abc9 -map +/techmap.v A:abc9_flop");
run("opt -nodffe -nosdff");
if (dff_mode || help_mode) {
if (!help_mode)
@ -369,6 +370,8 @@ struct Abc9Pass : public ScriptPass
if (saved_designs.count("$abc9_holes") || help_mode) {
run("design -stash $abc9");
run("design -load $abc9_holes");
if (help_mode) run("select =*");
else active_design->push_complete_selection();
run("techmap -wb -map %$abc9 -map +/techmap.v");
run("opt -purge");
run("aigmap");
@ -391,7 +394,7 @@ struct Abc9Pass : public ScriptPass
}
else {
auto selected_modules = active_design->selected_modules();
active_design->selection_stack.emplace_back(false);
active_design->push_empty_selection();
for (auto mod : selected_modules) {
if (mod->processes.size() > 0) {
@ -400,8 +403,9 @@ struct Abc9Pass : public ScriptPass
}
log_push();
active_design->selection().select(mod);
active_design->select(mod);
// this check does nothing because the above line adds the whole module to the selection
if (!active_design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
@ -452,7 +456,7 @@ struct Abc9Pass : public ScriptPass
log_pop();
}
active_design->selection_stack.pop_back();
active_design->pop_selection();
}
}

2
passes/techmap/abc9_ops.cc
View file

@ -454,7 +454,7 @@ void prep_bypass(RTLIL::Design *design)
void prep_dff(RTLIL::Design *design)
{
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false)));
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection::EmptySelection(design)));
auto &modules_sel = r.first->second;
for (auto module : design->selected_modules())

6
passes/techmap/abc_new.cc
View file

@ -139,7 +139,7 @@ struct AbcNewPass : public ScriptPass {
if (!help_mode) {
selected_modules = order_modules(active_design,
active_design->selected_whole_modules_warn());
active_design->selection_stack.emplace_back(false);
active_design->push_empty_selection();
} else {
selected_modules = {nullptr};
run("foreach module in selection");
@ -157,7 +157,7 @@ struct AbcNewPass : public ScriptPass {
exe_options = abc_exe_options;
log_header(active_design, "Mapping module '%s'.\n", log_id(mod));
log_push();
active_design->selection().select(mod);
active_design->select(mod);
}
std::string script_save;
@ -194,7 +194,7 @@ struct AbcNewPass : public ScriptPass {
}
if (!help_mode) {
active_design->selection_stack.pop_back();
active_design->pop_selection();
}
}
}

3
passes/techmap/aigmap.cc
View file

@ -171,8 +171,7 @@ struct AigmapPass : public Pass {
module->remove(cell);
if (select_mode) {
log_assert(!design->selection_stack.empty());
RTLIL::Selection& sel = design->selection_stack.back();
RTLIL::Selection& sel = design->selection();
sel.selected_members[module->name] = std::move(new_sel);
}

2
passes/techmap/clockgate.cc
View file

@ -333,7 +333,7 @@ struct ClockgatePass : public Pass {
dict<ClkNetInfo, GClkNetInfo> clk_nets;
int gated_flop_count = 0;
for (auto module : design->selected_whole_modules()) {
for (auto module : design->selected_unboxed_whole_modules()) {
for (auto cell : module->cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
continue;

2
passes/techmap/nlutmap.cc
View file

@ -42,7 +42,7 @@ struct NlutmapWorker
RTLIL::Selection get_selection()
{
RTLIL::Selection sel(false);
auto sel = RTLIL::Selection::EmptySelection(module->design);
for (auto cell : module->cells())
if (!mapped_cells.count(cell))
sel.select(module, cell);