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Merge pull request #5000 from YosysHQ/krys/re_refactor_selections

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N. Engelhardt 2025-04-10 16:06:36 +00:00 • committed by GitHub
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45 changed files with 1110 additions and 301 deletions
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1
passes/cmds/Makefile.inc
View file

@ -54,3 +54,4 @@ OBJS += passes/cmds/portarcs.o
OBJS += passes/cmds/wrapcell.o
OBJS += passes/cmds/setenv.o
OBJS += passes/cmds/abstract.o
OBJS += passes/cmds/test_select.o

2
passes/cmds/add.cc
View file

@ -102,7 +102,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
RTLIL::Module *mod = design->module(cell->type);
if (mod == nullptr)
continue;
if (!design->selected_whole_module(mod->name))
if (!mod->is_selected_whole())
continue;
if (mod->get_blackbox_attribute())
continue;

19
passes/cmds/design.cc
View file

@ -213,22 +213,15 @@ struct DesignPass : public Pass {
if (copy_from_design != design && argidx == args.size() && !import_mode)
cmd_error(args, argidx, "Missing selection.");
RTLIL::Selection sel;
if (argidx != args.size()) {
handle_extra_select_args(this, args, argidx, args.size(), copy_from_design);
sel = copy_from_design->selection_stack.back();
copy_from_design->selection_stack.pop_back();
argidx = args.size();
} else {
copy_from_design->push_complete_selection();
}
for (auto mod : copy_from_design->modules()) {
if (sel.selected_whole_module(mod->name)) {
copy_src_modules.push_back(mod);
continue;
}
if (sel.selected_module(mod->name))
log_cmd_error("Module %s is only partly selected.\n", log_id(mod->name));
}
for (auto mod : copy_from_design->selected_modules(RTLIL::SELECT_WHOLE_CMDERR, RTLIL::SB_ALL))
copy_src_modules.push_back(mod);
if (import_mode) {
std::vector<RTLIL::Module*> candidates;
@ -246,6 +239,8 @@ struct DesignPass : public Pass {
if (GetSize(candidates) == 1)
copy_src_modules = std::move(candidates);
}
copy_from_design->pop_selection();
}
extra_args(args, argidx, design, false);
@ -368,7 +363,7 @@ struct DesignPass : public Pass {
design->selection_vars.clear();
design->selected_active_module.clear();
design->selection_stack.push_back(RTLIL::Selection());
design->push_full_selection();
}
if (reset_mode || reset_vlog_mode || !load_name.empty() || push_mode || pop_mode)

2
passes/cmds/scc.cc
View file

@ -340,7 +340,7 @@ struct SccPass : public Pass {
int origSelectPos = design->selection_stack.size() - 1;
extra_args(args, argidx, design);
RTLIL::Selection newSelection(false);
auto newSelection = RTLIL::Selection::EmptySelection(design);
int scc_counter = 0;
for (auto mod : design->selected_modules())

287
passes/cmds/select.cc
View file

@ -141,24 +141,42 @@ static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, co
return match_attr(attributes, match_expr, std::string(), 0);
}
static void select_all(RTLIL::Design *design, RTLIL::Selection &lhs)
{
if (!lhs.selects_all())
return;
lhs.current_design = design;
lhs.selected_modules.clear();
for (auto mod : design->modules()) {
if (!lhs.selects_boxes && mod->get_blackbox_attribute())
continue;
lhs.selected_modules.insert(mod->name);
}
lhs.full_selection = false;
lhs.complete_selection = false;
}
static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
{
if (lhs.full_selection) {
lhs.full_selection = false;
lhs.selected_modules.clear();
lhs.selected_members.clear();
if (lhs.selects_all()) {
lhs.clear();
return;
}
if (lhs.selected_modules.size() == 0 && lhs.selected_members.size() == 0) {
lhs.full_selection = true;
if (lhs.selects_boxes)
lhs.complete_selection = true;
else
lhs.full_selection = true;
return;
}
RTLIL::Selection new_sel(false);
auto new_sel = RTLIL::Selection::EmptySelection();
for (auto mod : design->modules())
{
if (!lhs.selects_boxes && mod->get_blackbox_attribute())
continue;
if (lhs.selected_whole_module(mod->name))
continue;
if (!lhs.selected_module(mod->name)) {
@ -212,7 +230,7 @@ static void select_op_random(RTLIL::Design *design, RTLIL::Selection &lhs, int c
}
}
lhs = RTLIL::Selection(false);
lhs = RTLIL::Selection(false, lhs.selects_boxes, design);
while (!objects.empty() && count-- > 0)
{
@ -243,7 +261,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &lhs)
{
RTLIL::Selection new_sel(false);
RTLIL::Selection new_sel(false, lhs.selects_boxes, design);
for (auto mod : design->modules())
if (lhs.selected_module(mod->name))
for (auto cell : mod->cells())
@ -254,7 +272,7 @@ static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &
static void select_op_module_to_cells(RTLIL::Design *design, RTLIL::Selection &lhs)
{
RTLIL::Selection new_sel(false);
RTLIL::Selection new_sel(false, lhs.selects_boxes, design);
for (auto mod : design->modules())
for (auto cell : mod->cells())
if ((design->module(cell->type) != nullptr) && lhs.selected_whole_module(cell->type))
@ -274,6 +292,8 @@ static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
{
for (auto mod : design->modules())
{
if (!lhs.selects_boxes && mod->get_blackbox_attribute())
continue;
if (lhs.selected_whole_module(mod->name))
continue;
if (!lhs.selected_module(mod->name))
@ -292,18 +312,38 @@ static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
}
}
static void select_op_union(RTLIL::Design*, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
{
if (rhs.full_selection) {
lhs.full_selection = true;
lhs.selected_modules.clear();
lhs.selected_members.clear();
if (lhs.complete_selection)
return;
else if (rhs.complete_selection) {
lhs.complete_selection = true;
lhs.optimize(design);
return;
}
if (lhs.full_selection)
if (rhs.selects_boxes) {
if (lhs.full_selection) {
select_all(design, lhs);
}
lhs.selects_boxes = true;
}
else if (lhs.full_selection)
return;
if (rhs.full_selection) {
if (lhs.selects_boxes) {
auto new_rhs = RTLIL::Selection(rhs);
select_all(design, new_rhs);
for (auto mod : new_rhs.selected_modules)
lhs.selected_modules.insert(mod);
} else {
lhs.clear();
lhs.full_selection = true;
}
return;
}
for (auto &it : rhs.selected_members)
for (auto &it2 : it.second)
lhs.selected_members[it.first].insert(it2);
@ -316,21 +356,31 @@ static void select_op_union(RTLIL::Design*, RTLIL::Selection &lhs, const RTLIL::
static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
{
if (rhs.full_selection) {
lhs.full_selection = false;
lhs.selected_modules.clear();
lhs.selected_members.clear();
if (rhs.complete_selection) {
lhs.clear();
return;
}
if (lhs.full_selection) {
if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0)
return;
lhs.full_selection = false;
for (auto mod : design->modules())
lhs.selected_modules.insert(mod->name);
if (rhs.full_selection) {
if (lhs.selects_boxes) {
auto new_rhs = RTLIL::Selection(rhs);
select_all(design, new_rhs);
select_all(design, lhs);
for (auto mod : new_rhs.selected_modules) {
lhs.selected_modules.erase(mod);
lhs.selected_members.erase(mod);
}
} else {
lhs.clear();
}
return;
}
if (rhs.empty() || lhs.empty())
return;
select_all(design, lhs);
for (auto &it : rhs.selected_modules) {
lhs.selected_modules.erase(it);
lhs.selected_members.erase(it);
@ -366,38 +416,46 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
{
if (rhs.full_selection)
if (rhs.complete_selection)
return;
if (lhs.full_selection) {
lhs.full_selection = false;
for (auto mod : design->modules())
lhs.selected_modules.insert(mod->name);
if (rhs.full_selection && !lhs.selects_boxes)
return;
if (lhs.empty())
return;
if (rhs.empty()) {
lhs.clear();
return;
}
select_all(design, lhs);
std::vector<RTLIL::IdString> del_list;
for (auto &it : lhs.selected_modules)
if (rhs.selected_modules.count(it) == 0) {
if (rhs.selected_members.count(it) > 0)
for (auto &it2 : rhs.selected_members.at(it))
lhs.selected_members[it].insert(it2);
del_list.push_back(it);
}
for (auto mod_name : lhs.selected_modules) {
if (rhs.selected_whole_module(mod_name))
continue;
if (rhs.selected_module(mod_name))
for (auto memb_name : rhs.selected_members.at(mod_name))
lhs.selected_members[mod_name].insert(memb_name);
del_list.push_back(mod_name);
}
for (auto &it : del_list)
lhs.selected_modules.erase(it);
del_list.clear();
for (auto &it : lhs.selected_members) {
if (rhs.selected_modules.count(it.first) > 0)
if (rhs.selected_whole_module(it.first))
continue;
if (rhs.selected_members.count(it.first) == 0) {
if (!rhs.selected_module(it.first)) {
del_list.push_back(it.first);
continue;
}
std::vector<RTLIL::IdString> del_list2;
for (auto &it2 : it.second)
if (rhs.selected_members.at(it.first).count(it2) == 0)
if (!rhs.selected_member(it.first, it2))
del_list2.push_back(it2);
for (auto &it2 : del_list2)
it.second.erase(it2);
@ -610,9 +668,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
return;
if (sel.full_selection) {
sel.full_selection = false;
sel.selected_modules.clear();
sel.selected_members.clear();
sel.clear();
sel.selected_modules.insert(design->selected_active_module);
return;
}
@ -645,8 +701,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
if (arg[0] == '%') {
if (arg == "%") {
if (design->selection_stack.size() > 0)
work_stack.push_back(design->selection_stack.back());
work_stack.push_back(design->selection());
} else
if (arg == "%%") {
while (work_stack.size() > 1) {
@ -796,15 +851,16 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
}
}
work_stack.push_back(RTLIL::Selection());
bool full_selection = (arg == "*" && arg_mod == "*");
work_stack.push_back(RTLIL::Selection(full_selection, select_blackboxes, design));
RTLIL::Selection &sel = work_stack.back();
if (arg == "*" && arg_mod == "*" && select_blackboxes) {
if (sel.full_selection) {
if (sel.selects_boxes) sel.optimize(design);
select_filter_active_mod(design, work_stack.back());
return;
}
sel.full_selection = false;
for (auto mod : design->modules())
{
if (!select_blackboxes && mod->get_blackbox_attribute())
@ -945,38 +1001,33 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
for (auto &it : arg_mod_found) {
if (it.second == false && !disable_empty_warning) {
log_warning("Selection \"%s\" did not match any module.\n", it.first.c_str());
std::string selection_str = select_blackboxes ? "=" : "";
selection_str += it.first;
log_warning("Selection \"%s\" did not match any module.\n", selection_str.c_str());
}
}
for (auto &it : arg_memb_found) {
if (it.second == false && !disable_empty_warning) {
log_warning("Selection \"%s\" did not match any object.\n", it.first.c_str());
std::string selection_str = select_blackboxes ? "=" : "";
selection_str += it.first;
log_warning("Selection \"%s\" did not match any object.\n", selection_str.c_str());
}
}
}
static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel, bool whole_modules = false)
{
bool push_selection = &design->selection() != sel;
if (push_selection) design->push_selection(*sel);
std::string desc = "Selection contains:\n";
for (auto mod : design->modules())
for (auto mod : design->all_selected_modules())
{
if (sel->selected_module(mod->name)) {
if (whole_modules && sel->selected_whole_module(mod->name))
desc += stringf("%s\n", id2cstr(mod->name));
for (auto wire : mod->wires())
if (sel->selected_member(mod->name, wire->name))
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(wire->name));
for (auto &it : mod->memories)
if (sel->selected_member(mod->name, it.first))
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it.first));
for (auto cell : mod->cells())
if (sel->selected_member(mod->name, cell->name))
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(cell->name));
for (auto &it : mod->processes)
if (sel->selected_member(mod->name, it.first))
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it.first));
}
if (whole_modules && sel->selected_whole_module(mod->name))
desc += stringf("%s\n", id2cstr(mod->name));
for (auto it : mod->selected_members())
desc += stringf("%s/%s\n", id2cstr(mod->name), id2cstr(it->name));
}
if (push_selection) design->pop_selection();
return desc;
}
@ -1001,9 +1052,9 @@ void handle_extra_select_args(Pass *pass, const vector<string> &args, size_t arg
work_stack.pop_back();
}
if (work_stack.empty())
design->selection_stack.push_back(RTLIL::Selection(false));
design->push_empty_selection();
else
design->selection_stack.push_back(work_stack.back());
design->push_selection(work_stack.back());
}
// extern decl. in register.h
@ -1017,7 +1068,7 @@ RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *des
work_stack.pop_back();
}
if (work_stack.empty())
return RTLIL::Selection(false);
return RTLIL::Selection::EmptySelection(design);
return work_stack.back();
}
@ -1390,7 +1441,7 @@ struct SelectPass : public Pass {
if (f.fail())
log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno));
RTLIL::Selection sel(false);
auto sel = RTLIL::Selection::EmptySelection(design);
string line;
while (std::getline(f, line)) {
@ -1431,7 +1482,7 @@ struct SelectPass : public Pass {
log_cmd_error("Option -unset can not be combined with -list, -write, -count, -set, %s.\n", common_flagset);
if (work_stack.size() == 0 && got_module) {
RTLIL::Selection sel;
auto sel = RTLIL::Selection::FullSelection(design);
select_filter_active_mod(design, sel);
work_stack.push_back(sel);
}
@ -1441,16 +1492,16 @@ struct SelectPass : public Pass {
work_stack.pop_back();
}
log_assert(design->selection_stack.size() > 0);
log_assert(!design->selection_stack.empty());
if (clear_mode) {
design->selection_stack.back() = RTLIL::Selection(true);
design->selection() = RTLIL::Selection::FullSelection(design);
design->selected_active_module = std::string();
return;
}
if (none_mode) {
design->selection_stack.back() = RTLIL::Selection(false);
design->selection() = RTLIL::Selection::EmptySelection(design);
return;
}
@ -1465,28 +1516,17 @@ struct SelectPass : public Pass {
if (f == nullptr)
log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno));
}
RTLIL::Selection *sel = &design->selection_stack.back();
if (work_stack.size() > 0)
sel = &work_stack.back();
design->push_selection(work_stack.back());
RTLIL::Selection *sel = &design->selection();
sel->optimize(design);
for (auto mod : design->modules())
for (auto mod : design->all_selected_modules())
{
if (sel->selected_whole_module(mod->name) && list_mode)
log("%s\n", id2cstr(mod->name));
if (sel->selected_module(mod->name) && !list_mod_mode) {
for (auto wire : mod->wires())
if (sel->selected_member(mod->name, wire->name))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(wire->name))
for (auto &it : mod->memories)
if (sel->selected_member(mod->name, it.first))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it.first))
for (auto cell : mod->cells())
if (sel->selected_member(mod->name, cell->name))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(cell->name))
for (auto &it : mod->processes)
if (sel->selected_member(mod->name, it.first))
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it.first))
}
if (!list_mod_mode)
for (auto it : mod->selected_members())
LOG_OBJECT("%s/%s\n", id2cstr(mod->name), id2cstr(it->name))
}
if (count_mode)
{
@ -1495,6 +1535,8 @@ struct SelectPass : public Pass {
}
if (f != nullptr)
fclose(f);
if (work_stack.size() > 0)
design->pop_selection();
#undef LOG_OBJECT
return;
}
@ -1503,8 +1545,8 @@ struct SelectPass : public Pass {
{
if (work_stack.size() == 0)
log_cmd_error("Nothing to add to selection.\n");
select_op_union(design, design->selection_stack.back(), work_stack.back());
design->selection_stack.back().optimize(design);
select_op_union(design, design->selection(), work_stack.back());
design->selection().optimize(design);
return;
}
@ -1512,8 +1554,8 @@ struct SelectPass : public Pass {
{
if (work_stack.size() == 0)
log_cmd_error("Nothing to delete from selection.\n");
select_op_diff(design, design->selection_stack.back(), work_stack.back());
design->selection_stack.back().optimize(design);
select_op_diff(design, design->selection(), work_stack.back());
design->selection().optimize(design);
return;
}
@ -1553,23 +1595,13 @@ struct SelectPass : public Pass {
if (work_stack.size() == 0)
log_cmd_error("No selection to check.\n");
RTLIL::Selection *sel = &work_stack.back();
design->push_selection(*sel);
sel->optimize(design);
for (auto mod : design->modules())
if (sel->selected_module(mod->name)) {
module_count++;
for (auto wire : mod->wires())
if (sel->selected_member(mod->name, wire->name))
total_count++;
for (auto &it : mod->memories)
if (sel->selected_member(mod->name, it.first))
total_count++;
for (auto cell : mod->cells())
if (sel->selected_member(mod->name, cell->name))
total_count++;
for (auto &it : mod->processes)
if (sel->selected_member(mod->name, it.first))
total_count++;
}
for (auto mod : design->all_selected_modules()) {
module_count++;
for ([[maybe_unused]] auto member_name : mod->selected_members())
total_count++;
}
if (assert_modcount >= 0 && assert_modcount != module_count)
{
log_error("Assertion failed: selection contains %d modules instead of the asserted %d:%s\n",
@ -1593,13 +1625,14 @@ struct SelectPass : public Pass {
log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s",
total_count, assert_min, sel_str.c_str(), desc.c_str());
}
design->pop_selection();
return;
}
if (!set_name.empty())
{
if (work_stack.size() == 0)
design->selection_vars[set_name] = RTLIL::Selection(false);
design->selection_vars[set_name] = RTLIL::Selection::EmptySelection(design);
else
design->selection_vars[set_name] = work_stack.back();
return;
@ -1613,7 +1646,7 @@ struct SelectPass : public Pass {
}
if (work_stack.size() == 0) {
RTLIL::Selection &sel = design->selection_stack.back();
RTLIL::Selection &sel = design->selection();
if (sel.full_selection)
log("*\n");
for (auto &it : sel.selected_modules)
@ -1624,8 +1657,8 @@ struct SelectPass : public Pass {
return;
}
design->selection_stack.back() = work_stack.back();
design->selection_stack.back().optimize(design);
design->selection() = work_stack.back();
design->selection().optimize(design);
}
} SelectPass;
@ -1665,7 +1698,8 @@ struct CdPass : public Pass {
log_cmd_error("Invalid number of arguments.\n");
if (args.size() == 1 || args[1] == "/") {
design->selection_stack.back() = RTLIL::Selection(true);
design->pop_selection();
design->push_full_selection();
design->selected_active_module = std::string();
return;
}
@ -1674,7 +1708,8 @@ struct CdPass : public Pass {
{
string modname = design->selected_active_module;
design->selection_stack.back() = RTLIL::Selection(true);
design->pop_selection();
design->push_full_selection();
design->selected_active_module = std::string();
while (1)
@ -1691,9 +1726,10 @@ struct CdPass : public Pass {
continue;
design->selected_active_module = modname;
design->selection_stack.back() = RTLIL::Selection();
select_filter_active_mod(design, design->selection_stack.back());
design->selection_stack.back().optimize(design);
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
design->selection().optimize(design);
return;
}
@ -1710,9 +1746,10 @@ struct CdPass : public Pass {
if (design->module(modname) != nullptr) {
design->selected_active_module = modname;
design->selection_stack.back() = RTLIL::Selection();
select_filter_active_mod(design, design->selection_stack.back());
design->selection_stack.back().optimize(design);
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
design->selection().optimize(design);
return;
}
@ -1759,7 +1796,7 @@ struct LsPass : public Pass {
{
std::vector<IdString> matches;
for (auto mod : design->selected_modules())
for (auto mod : design->all_selected_modules())
matches.push_back(mod->name);
if (!matches.empty()) {

34
passes/cmds/setattr.cc
View file

@ -96,32 +96,16 @@ struct SetattrPass : public Pass {
}
extra_args(args, argidx, design);
for (auto module : design->modules())
for (auto module : design->all_selected_modules())
{
if (flag_mod) {
if (design->selected_whole_module(module->name))
if (module->is_selected_whole())
do_setunset(module->attributes, setunset_list);
continue;
}
if (!design->selected(module))
continue;
for (auto wire : module->wires())
if (design->selected(module, wire))
do_setunset(wire->attributes, setunset_list);
for (auto &it : module->memories)
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);
for (auto cell : module->cells())
if (design->selected(module, cell))
do_setunset(cell->attributes, setunset_list);
for (auto &it : module->processes)
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);
for (auto memb : module->selected_members())
do_setunset(memb->attributes, setunset_list);
}
}
} SetattrPass;
@ -152,16 +136,8 @@ struct WbflipPass : public Pass {
}
extra_args(args, argidx, design);
for (Module *module : design->modules())
{
if (!design->selected(module))
continue;
if (module->get_bool_attribute(ID::blackbox))
continue;
for (auto *module : design->selected_modules(RTLIL::SELECT_ALL, RTLIL::SB_EXCL_BB_ONLY))
module->set_bool_attribute(ID::whitebox, !module->get_bool_attribute(ID::whitebox));
}
}
} WbflipPass;

8
passes/cmds/show.cc
View file

@ -802,8 +802,8 @@ struct ShowPass : public Pass {
std::pair<std::string, RTLIL::Selection> data;
data.first = args[++argidx], argidx++;
handle_extra_select_args(this, args, argidx, argidx+1, design);
data.second = design->selection_stack.back();
design->selection_stack.pop_back();
data.second = design->selection();
design->pop_selection();
color_selections.push_back(data);
continue;
}
@ -811,8 +811,8 @@ struct ShowPass : public Pass {
std::pair<std::string, RTLIL::Selection> data;
data.first = args[++argidx], argidx++;
handle_extra_select_args(this, args, argidx, argidx+1, design);
data.second = design->selection_stack.back();
design->selection_stack.pop_back();
data.second = design->selection();
design->pop_selection();
label_selections.push_back(data);
continue;
}

2
passes/cmds/stat.cc
View file

@ -468,7 +468,7 @@ struct StatPass : public Pass {
first_module = false;
} else {
log("\n");
log("=== %s%s ===\n", log_id(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
log("=== %s%s ===\n", log_id(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
log("\n");
data.log_data(mod->name, false);
}

172
passes/cmds/test_select.cc Normal file
View file

@ -0,0 +1,172 @@
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct TestSelectPass : public Pass {
TestSelectPass() : Pass("test_select", "call internal selection methods on design for testing purposes") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" test_select [options]\n");
log("\n");
log("Test semantics of internal 'RTLIL::Design::selected_modules()' by modifying the\n");
log("current selection to only include the results of the call.\n");
log("\n");
log("Includes partially selected modules by default, use one of the following options\n");
log("to remove them instead:\n");
log("\n");
log(" -whole_only\n");
log("\n");
log(" -whole_warn\n");
log(" -whole_err\n");
log(" -whole_cmderr\n");
log(" remove partially selected modules, raising warning, error, or cmd error\n");
log("\n");
log(" test_select -unboxed_only [options]\n");
log("\n");
log("Remove boxed modules from selection.\n");
log("\n");
log(" -include_wb\n");
log(" don't remove white boxes from selection\n");
log("\n");
log(" -warn_boxes\n");
log(" -err_boxes\n");
log(" -cmderr_boxes\n");
log(" raise warning, error, or cmd error if a box is removed\n");
log("\n");
}
void execute(vector<string> args, RTLIL::Design *design) override
{
log_header(design, "Executing TEST_SELECTION pass.\n");
bool whole_only = false;
bool whole_warn = false;
bool whole_err = false;
bool whole_cmderr = false;
int whole_opts = 0;
bool warn_boxes = false;
bool err_boxes = false;
bool cmderr_boxes = false;
int box_level = 0;
bool unboxed_only = false;
bool include_wb = false;
int argidx;
for (argidx = 1; argidx < GetSize(args); argidx++)
{
if (args[argidx] == "-whole_only") {
whole_only = true;
whole_opts++;
continue;
}
if (args[argidx] == "-whole_warn") {
whole_warn = true;
whole_opts++;
continue;
}
if (args[argidx] == "-whole_err") {
whole_err = true;
whole_opts++;
continue;
}
if (args[argidx] == "-whole_cmderr") {
whole_cmderr = true;
whole_opts++;
continue;
}
if (args[argidx] == "-warn_boxes") {
warn_boxes = true;
box_level++;
continue;
}
if (args[argidx] == "-err_boxes") {
err_boxes = true;
box_level++;
continue;
}
if (args[argidx] == "-cmderr_boxes") {
cmderr_boxes = true;
box_level++;
continue;
}
if (args[argidx] == "-unboxed_only") {
unboxed_only = true;
continue;
}
if (args[argidx] == "-include_wb") {
include_wb = true;
continue;
}
break;
}
if (whole_opts > 1)
log_cmd_error("Only one of -whole_only, -whole_warn, -whole_err, or -whole_cmderr may be selected.\n");
if (include_wb && !unboxed_only)
log_cmd_error("-include_wb option requires -unboxed_only.\n");
if (box_level > 0 && !unboxed_only)
log_cmd_error("-*_boxes options require -unboxed_only.\n");
if (box_level > 1)
log_cmd_error("Only one of -warn_boxes, -err_boxes, or -cmderr_boxes may be selected.\n");
extra_args(args, argidx, design, false);
// construct enums
RTLIL::SelectPartials partials;
if (whole_only)
partials = RTLIL::SELECT_WHOLE_ONLY;
else if (whole_warn)
partials = RTLIL::SELECT_WHOLE_WARN;
else if (whole_err)
partials = RTLIL::SELECT_WHOLE_ERR;
else if (whole_cmderr)
partials = RTLIL::SELECT_WHOLE_CMDERR;
else
partials = RTLIL::SELECT_ALL;
char boxes = RTLIL::SB_ALL;
if (warn_boxes) boxes |= RTLIL::SB_WARN;
if (err_boxes) boxes |= RTLIL::SB_ERR;
if (cmderr_boxes) boxes |= RTLIL::SB_CMDERR;
if (unboxed_only) boxes |= RTLIL::SB_UNBOXED_ONLY;
if (include_wb) boxes |= RTLIL::SB_INCL_WB;
// get sub selection and store the results
auto sub_sel = design->selected_modules(partials, (RTLIL::SelectBoxes)boxes);
pool<RTLIL::IdString> selected_modules;
dict<RTLIL::IdString, pool<RTLIL::NamedObject*>> selected_members;
for (auto *mod : sub_sel) {
if (mod->is_selected_whole()) {
log_debug(" Adding %s.\n", id2cstr(mod->name));
selected_modules.insert(mod->name);
} else for (auto *memb : mod->selected_members()) {
log_debug(" Adding %s.%s.\n", id2cstr(mod->name), id2cstr(memb->name));
selected_members[mod->name].insert(memb);
}
}
// fully reset current selection
design->selection() = RTLIL::Selection::EmptySelection(design);
// add back sub selection
for (auto modname : selected_modules)
design->selection().select(design->module(modname));
for (auto &it : selected_members) {
auto mod = design->module(it.first);
for (auto memb : it.second)
design->selection().select(mod, memb);
}
// optimize
design->selection().optimize(design);
}
} TestSelectPass;
PRIVATE_NAMESPACE_END

4
passes/cmds/viz.cc
View file

@ -950,8 +950,8 @@ struct VizPass : public Pass {
auto type = arg == "-g" || arg == "-G" ? VizConfig::TYPE_G :
arg == "-u" || arg == "-U" ? VizConfig::TYPE_U :
arg == "-x" || arg == "-X" ? VizConfig::TYPE_X : VizConfig::TYPE_S;
config.groups.push_back({type, design->selection_stack.back()});
design->selection_stack.pop_back();
config.groups.push_back({type, design->selection()});
design->pop_selection();
continue;
}
if (arg == "-0" || arg == "-1" || arg == "-2" || arg == "-3" || arg == "-4" ||

2
passes/hierarchy/submod.cc
View file

@ -246,7 +246,7 @@ struct SubmodWorker
SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, bool hidden_mode = false, std::string opt_name = std::string()) :
design(design), module(module), sigmap(module), copy_mode(copy_mode), hidden_mode(hidden_mode), opt_name(opt_name)
{
if (!design->selected_whole_module(module->name) && opt_name.empty())
if (!module->is_selected_whole() && opt_name.empty())
return;
if (module->processes.size() > 0) {

2
passes/opt/opt_clean.cc
View file

@ -734,7 +734,7 @@ struct CleanPass : public Pass {
count_rm_cells = 0;
count_rm_wires = 0;
for (auto module : design->selected_whole_modules()) {
for (auto module : design->selected_unboxed_whole_modules()) {
if (module->has_processes())
continue;
rmunused_module(module, purge_mode, ys_debug(), true);

2
passes/sat/cutpoint.cc
View file

@ -57,7 +57,7 @@ struct CutpointPass : public Pass {
for (auto module : design->selected_modules())
{
if (design->selected_whole_module(module->name)) {
if (module->is_selected_whole()) {
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
module->new_connections(std::vector<RTLIL::SigSig>());
for (auto cell : vector<Cell*>(module->cells()))

4
passes/sat/sim.cc
View file

@ -2887,7 +2887,7 @@ struct SimPass : public Pass {
if (!top_mod)
log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
} else {
auto mods = design->selected_whole_modules();
auto mods = design->selected_unboxed_whole_modules();
if (GetSize(mods) != 1)
log_cmd_error("Only one top module must be selected.\n");
top_mod = mods.front();
@ -3016,7 +3016,7 @@ struct Fst2TbPass : public Pass {
if (!top_mod)
log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
} else {
auto mods = design->selected_whole_modules();
auto mods = design->selected_unboxed_whole_modules();
if (GetSize(mods) != 1)
log_cmd_error("Only one top module must be selected.\n");
top_mod = mods.front();

14
passes/techmap/abc9.cc
View file

@ -306,9 +306,10 @@ struct Abc9Pass : public ScriptPass
}
run("design -stash $abc9");
run("design -load $abc9_map");
run("proc");
if (help_mode) run("select =*");
else active_design->push_complete_selection();
run("wbflip");
run("techmap -wb -map %$abc9 -map +/techmap.v A:abc9_flop");
run("techmap -autoproc -wb -map %$abc9 -map +/techmap.v A:abc9_flop");
run("opt -nodffe -nosdff");
if (dff_mode || help_mode) {
if (!help_mode)
@ -369,6 +370,8 @@ struct Abc9Pass : public ScriptPass
if (saved_designs.count("$abc9_holes") || help_mode) {
run("design -stash $abc9");
run("design -load $abc9_holes");
if (help_mode) run("select =*");
else active_design->push_complete_selection();
run("techmap -wb -map %$abc9 -map +/techmap.v");
run("opt -purge");
run("aigmap");
@ -391,7 +394,7 @@ struct Abc9Pass : public ScriptPass
}
else {
auto selected_modules = active_design->selected_modules();
active_design->selection_stack.emplace_back(false);
active_design->push_empty_selection();
for (auto mod : selected_modules) {
if (mod->processes.size() > 0) {
@ -400,8 +403,9 @@ struct Abc9Pass : public ScriptPass
}
log_push();
active_design->selection().select(mod);
active_design->select(mod);
// this check does nothing because the above line adds the whole module to the selection
if (!active_design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
@ -452,7 +456,7 @@ struct Abc9Pass : public ScriptPass
log_pop();
}
active_design->selection_stack.pop_back();
active_design->pop_selection();
}
}

2
passes/techmap/abc9_ops.cc
View file

@ -454,7 +454,7 @@ void prep_bypass(RTLIL::Design *design)
void prep_dff(RTLIL::Design *design)
{
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false)));
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection::EmptySelection(design)));
auto &modules_sel = r.first->second;
for (auto module : design->selected_modules())

6
passes/techmap/abc_new.cc
View file

@ -139,7 +139,7 @@ struct AbcNewPass : public ScriptPass {
if (!help_mode) {
selected_modules = order_modules(active_design,
active_design->selected_whole_modules_warn());
active_design->selection_stack.emplace_back(false);
active_design->push_empty_selection();
} else {
selected_modules = {nullptr};
run("foreach module in selection");
@ -157,7 +157,7 @@ struct AbcNewPass : public ScriptPass {
exe_options = abc_exe_options;
log_header(active_design, "Mapping module '%s'.\n", log_id(mod));
log_push();
active_design->selection().select(mod);
active_design->select(mod);
}
std::string script_save;
@ -194,7 +194,7 @@ struct AbcNewPass : public ScriptPass {
}
if (!help_mode) {
active_design->selection_stack.pop_back();
active_design->pop_selection();
}
}
}

3
passes/techmap/aigmap.cc
View file

@ -171,8 +171,7 @@ struct AigmapPass : public Pass {
module->remove(cell);
if (select_mode) {
log_assert(!design->selection_stack.empty());
RTLIL::Selection& sel = design->selection_stack.back();
RTLIL::Selection& sel = design->selection();
sel.selected_members[module->name] = std::move(new_sel);
}

2
passes/techmap/clockgate.cc
View file

@ -333,7 +333,7 @@ struct ClockgatePass : public Pass {
dict<ClkNetInfo, GClkNetInfo> clk_nets;
int gated_flop_count = 0;
for (auto module : design->selected_whole_modules()) {
for (auto module : design->selected_unboxed_whole_modules()) {
for (auto cell : module->cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
continue;

2
passes/techmap/nlutmap.cc
View file

@ -42,7 +42,7 @@ struct NlutmapWorker
RTLIL::Selection get_selection()
{
RTLIL::Selection sel(false);
auto sel = RTLIL::Selection::EmptySelection(module->design);
for (auto cell : module->cells())
if (!mapped_cells.count(cell))
sel.select(module, cell);