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opt_merge: test more kinds of cells

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This commit is contained in:
Emil J. Tywoniak 2025-03-10 12:56:21 +01:00
parent ae7a97cc2d
commit 33bfc9d19c
1 changed files with 98 additions and 6 deletions
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104
tests/opt/opt_merge_basic.ys
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@ -19,7 +19,7 @@ module top(A, B, C, X, Y);
input [7:0] A, B, C;
output [7:0] X, Y;
assign X = A + B;
assign Y = A + C;
assign Y = A + C; // <- look here
endmodule
EOT
# Reject on a different input
@ -45,10 +45,9 @@ select -assert-count 1 t:$reduce_xor
design -reset
read_verilog -icells <<EOT
module top(A, B, X, Y);
input [7:0] A;
input [7:0] B;
input [7:0] A, B;
output X, Y;
\$reduce_or #(
\$reduce_xor #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd16),
.Y_WIDTH(32'd1),
@ -56,7 +55,7 @@ output X, Y;
.A({A, B}), // <- look here
.Y(X)
);
\$reduce_or #(
\$reduce_xor #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd16),
.Y_WIDTH(32'd1),
@ -66,9 +65,102 @@ output X, Y;
);
endmodule
EOT
# Unary
# Unary is sorted
opt_expr
select -assert-count 2 t:$reduce_xor
equiv_opt -assert opt_merge
design -load postopt
select -assert-count 1 t:$reduce_xor
design -reset
read_verilog -icells <<EOT
module top(A, B, X, Y);
input [7:0] A, B;
output X, Y;
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd24),
.Y_WIDTH(32'd1),
) one (
.A({A, B, B}), // <- look here
.Y(X)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd24),
.Y_WIDTH(32'd1),
) other (
.A({A, A, B}), // <- look here
.Y(Y)
);
endmodule
EOT
# Unary is unified when valid
opt_expr
select -assert-count 2 t:$reduce_or
equiv_opt -assert opt_merge
design -load postopt
select -assert-count 1 t:$reduce_or
design -reset
read_verilog -icells <<EOT
module top(A, B, X, Y);
input [7:0] A, B;
output X, Y;
\$reduce_xor #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd24),
.Y_WIDTH(32'd1),
) one (
.A({A, B, B}), // <- look here
.Y(X)
);
\$reduce_xor #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd24),
.Y_WIDTH(32'd1),
) other (
.A({A, A, B}), // <- look here
.Y(Y)
);
endmodule
EOT
# Unary isn't unified when that would be invalid
opt_expr
select -assert-count 2 t:$reduce_xor
equiv_opt -assert opt_merge
design -load postopt
select -assert-count 2 t:$reduce_xor
# TODO pmux
design -reset
read_verilog <<EOT
module top(A, B, X, Y);
input [7:0] A, B;
output X, Y;
assign X = A > B;
assign Y = A > B;
endmodule
EOT
# Exercise the general case in hash_cell_inputs - accept
opt_expr
select -assert-count 2 t:$gt
equiv_opt -assert opt_merge
design -load postopt
select -assert-count 1 t:$gt
design -reset
read_verilog <<EOT
module top(A, B, C, X, Y);
input [7:0] A, B, C;
output X, Y;
assign X = A > B;
assign Y = A > C; // <- look here
endmodule
EOT
# Exercise the general case in hash_cell_inputs - reject
opt_expr
select -assert-count 2 t:$gt
opt_merge
select -assert-count 2 t:$gt