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xaiger: add testcase

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Eddie Hung 2020-05-24 08:48:23 -07:00
parent d64df21630
commit 33b03ce904
1 changed files with 13 additions and 0 deletions
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tests/various/xaiger.ys Normal file
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read_verilog <<EOT
module top(input a, b, output c);
bb #(1) bb();
endmodule
module bb(input a, b, output c);
parameter p = 0;
assign c = a ^ b;
endmodule
EOT
blackbox bb
hierarchy
write_xaiger /dev/null