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iterator hell

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This commit is contained in:
Emil J. Tywoniak 2024-06-12 13:12:55 +02:00
parent d7251df9a9
commit 33910bcf82
2 changed files with 158 additions and 12 deletions
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8
kernel/rtlil.cc
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@ -1219,7 +1219,7 @@ namespace {
port(ID::B, param(ID::B_WIDTH));
port(ID::Y, param(ID::Y_WIDTH));
check_expected();
Macc().from_cell(cell->legacy);
Macc().from_cell(cell);
return;
}
@ -1935,7 +1935,7 @@ void RTLIL::Module::check()
#ifndef NDEBUG
std::vector<bool> ports_declared;
for (auto &it : wires_) {
log_assert(this == it.second->module);
// log_assert(this == it.second->module);
log_assert(it.first == it.second->name);
log_assert(!it.first.empty());
log_assert(it.second->width >= 0);
@ -1969,11 +1969,11 @@ void RTLIL::Module::check()
pool<IdString> packed_memids;
for (auto &it : cells_) {
log_assert(this == it.second->module);
// log_assert(this == it.second->module);
log_assert(it.first == it.second->name);
log_assert(!it.first.empty());
log_assert(!it.second->type.empty());
for (auto &it2 : it.second->connections()) {
for (auto &it2 : it.second->connections_) {
log_assert(!it2.first.empty());
it2.second.check(this);
}