mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 09:34:09 +00:00
Merge pull request #2178 from boqwxp/design-select
rtlil: Add `Design::select()` for selecting whole modules
This commit is contained in:
commit
338ecbe02f
|
@ -1061,6 +1061,13 @@ struct RTLIL::Design
|
||||||
return selected_member(module->name, member->name);
|
return selected_member(module->name, member->name);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
template<typename T1> void select(T1 *module) {
|
||||||
|
if (selection_stack.size() > 0) {
|
||||||
|
RTLIL::Selection &sel = selection_stack.back();
|
||||||
|
sel.select(module);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
|
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
|
||||||
if (selection_stack.size() > 0) {
|
if (selection_stack.size() > 0) {
|
||||||
RTLIL::Selection &sel = selection_stack.back();
|
RTLIL::Selection &sel = selection_stack.back();
|
||||||
|
|
Loading…
Reference in a new issue