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	dffinit: Refactor to use FfInitVals.
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					 1 changed files with 7 additions and 41 deletions
				
			
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			@ -19,6 +19,7 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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			@ -94,29 +95,10 @@ struct DffinitPass : public Pass {
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		for (auto module : design->selected_modules())
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		{
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			SigMap sigmap(module);
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			dict<SigBit, State> init_bits;
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			pool<SigBit> cleanup_bits;
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			pool<SigBit> used_bits;
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			for (auto wire : module->selected_wires()) {
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				if (wire->attributes.count(ID::init)) {
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					Const value = wire->attributes.at(ID::init);
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					for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
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						if (value[i] != State::Sx)
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							init_bits[sigmap(SigBit(wire, i))] = value[i];
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				}
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				if (wire->port_output)
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					for (auto bit : sigmap(wire))
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						used_bits.insert(bit);
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			}
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			FfInitVals initvals(&sigmap, module);
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			for (auto cell : module->selected_cells())
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			{
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				for (auto it : cell->connections())
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					if (!cell->known() || cell->input(it.first))
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						for (auto bit : sigmap(it.second))
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							used_bits.insert(bit);
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				if (ff_types.count(cell->type) == 0)
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					continue;
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			@ -131,17 +113,18 @@ struct DffinitPass : public Pass {
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					if (cell->hasParam(it.second))
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						value = cell->getParam(it.second);
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					Const initval = initvals(sig);
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					initvals.remove_init(sig);
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					for (int i = 0; i < GetSize(sig); i++) {
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						if (init_bits.count(sig[i]) == 0)
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						if (initval[i] == State::Sx)
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							continue;
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						while (GetSize(value.bits) <= i)
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							value.bits.push_back(State::S0);
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						if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i]))
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						if (noreinit && value.bits[i] != State::Sx && value.bits[i] != initval[i])
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							log_error("Trying to assign a different init value for %s.%s.%s which technically "
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									"have a conflicted init value.\n",
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									log_id(module), log_id(cell), log_id(it.second));
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						value.bits[i] = init_bits.at(sig[i]);
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						cleanup_bits.insert(sig[i]);
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						value.bits[i] = initval[i];
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					}
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					if (highlow_mode && GetSize(value) != 0) {
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			@ -161,23 +144,6 @@ struct DffinitPass : public Pass {
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					}
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				}
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			}
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			for (auto wire : module->selected_wires())
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				if (wire->attributes.count(ID::init)) {
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					Const &value = wire->attributes.at(ID::init);
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					bool do_cleanup = true;
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					for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
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						SigBit bit = sigmap(SigBit(wire, i));
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						if (cleanup_bits.count(bit) || !used_bits.count(bit))
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							value[i] = State::Sx;
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						else if (value[i] != State::Sx)
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							do_cleanup = false;
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					}
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					if (do_cleanup) {
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						log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
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						wire->attributes.erase(ID::init);
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					}
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				}
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		}
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	}
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} DffinitPass;
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