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dffinit: Refactor to use FfInitVals.

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This commit is contained in:
Marcelina Kościelnicka 2020-07-19 02:06:25 +02:00
parent 1c8483b7dd
commit 336b8c7786
1 changed files with 7 additions and 41 deletions
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48
passes/techmap/dffinit.cc
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@ -19,6 +19,7 @@
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/ffinit.h"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
@ -94,29 +95,10 @@ struct DffinitPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
SigMap sigmap(module); SigMap sigmap(module);
dict<SigBit, State> init_bits; FfInitVals initvals(&sigmap, module);
pool<SigBit> cleanup_bits;
pool<SigBit> used_bits;
for (auto wire : module->selected_wires()) {
if (wire->attributes.count(ID::init)) {
Const value = wire->attributes.at(ID::init);
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
if (value[i] != State::Sx)
init_bits[sigmap(SigBit(wire, i))] = value[i];
}
if (wire->port_output)
for (auto bit : sigmap(wire))
used_bits.insert(bit);
}
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
for (auto it : cell->connections())
if (!cell->known() || cell->input(it.first))
for (auto bit : sigmap(it.second))
used_bits.insert(bit);
if (ff_types.count(cell->type) == 0) if (ff_types.count(cell->type) == 0)
continue; continue;
@ -131,17 +113,18 @@ struct DffinitPass : public Pass {
if (cell->hasParam(it.second)) if (cell->hasParam(it.second))
value = cell->getParam(it.second); value = cell->getParam(it.second);
Const initval = initvals(sig);
initvals.remove_init(sig);
for (int i = 0; i < GetSize(sig); i++) { for (int i = 0; i < GetSize(sig); i++) {
if (init_bits.count(sig[i]) == 0) if (initval[i] == State::Sx)
continue; continue;
while (GetSize(value.bits) <= i) while (GetSize(value.bits) <= i)
value.bits.push_back(State::S0); value.bits.push_back(State::S0);
if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i])) if (noreinit && value.bits[i] != State::Sx && value.bits[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically " log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n", "have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second)); log_id(module), log_id(cell), log_id(it.second));
value.bits[i] = init_bits.at(sig[i]); value.bits[i] = initval[i];
cleanup_bits.insert(sig[i]);
} }
if (highlow_mode && GetSize(value) != 0) { if (highlow_mode && GetSize(value) != 0) {
@ -161,23 +144,6 @@ struct DffinitPass : public Pass {
} }
} }
} }
for (auto wire : module->selected_wires())
if (wire->attributes.count(ID::init)) {
Const &value = wire->attributes.at(ID::init);
bool do_cleanup = true;
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (cleanup_bits.count(bit) || !used_bits.count(bit))
value[i] = State::Sx;
else if (value[i] != State::Sx)
do_cleanup = false;
}
if (do_cleanup) {
log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
wire->attributes.erase(ID::init);
}
}
} }
} }
} DffinitPass; } DffinitPass;