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abc: remove -lut/-luts

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This commit is contained in:
Lofty 2026-03-24 12:59:17 +00:00
parent 5fd39ff3e1
commit 3369cc525f
20 changed files with 35 additions and 118 deletions
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2
tests/arch/anlogic/mux.ys
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@ -27,7 +27,7 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-max 3 t:AL_MAP_LUT3
select -assert-max 3 t:AL_MAP_LUT4
select -assert-max 4 t:AL_MAP_LUT4
select -assert-max 1 t:AL_MAP_LUT5
select -assert-max 1 t:AL_MAP_LUT6

2
tests/arch/efinix/mux.ys
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@ -36,6 +36,6 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:EFX_LUT4
select -assert-max 13 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D

2
tests/arch/gatemate/fsm.ys
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@ -16,5 +16,5 @@ select -assert-count 1 t:CC_BUFG
select -assert-count 6 t:CC_DFF
select -assert-max 5 t:CC_LUT2
select -assert-max 6 t:CC_LUT3
select -assert-max 9 t:CC_LUT4
select -assert-max 11 t:CC_LUT4
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D

13
tests/arch/gatemate/mux.ys
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@ -7,10 +7,8 @@ proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-max 1 t:CC_LUT2
select -assert-max 2 t:CC_LUT4
select -assert-max 1 t:CC_MX2
select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D
select -assert-max 3 t:CC_LUT3
select -assert-none t:CC_LUT3 %% t:* %D
design -load read
hierarchy -top mux8
@ -18,7 +16,6 @@ proc
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-max 1 t:CC_LUT3
select -assert-max 5 t:CC_LUT4
select -assert-max 1 t:CC_MX2
select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D
select -assert-max 3 t:CC_LUT3
select -assert-max 3 t:CC_LUT4
select -assert-none t:CC_LUT3 t:CC_LUT4 %% t:* %D

2
tests/arch/machxo2/lutram.ys
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@ -11,7 +11,7 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite
design -load postopt
cd lutram_1w1r
select -assert-count 20 t:LUT4
select -assert-count 28 t:LUT4
select -assert-count 8 t:TRELLIS_DPR16X4
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D

6
tests/arch/machxo2/mux.ys
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@ -15,7 +15,7 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4
select -assert-count 3 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
@ -25,7 +25,7 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT4
select -assert-count 6 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D
@ -35,6 +35,6 @@ proc
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_lattice -family xo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 12 t:LUT4
select -assert-max 13 t:LUT4
select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D

2
tests/arch/nexus/counter.ys
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@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module
stat
select -assert-count 5 t:CCU2
select -assert-count 8 t:FD1P3DX
select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D
select -assert-none t:CCU2 t:FD1P3DX t:IB t:OB t:INV t:VLO t:VHI %% t:* %D

5
tests/arch/xilinx/fsm.ys
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@ -30,8 +30,7 @@ cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 1 t:LUT1
select -assert-max 1 t:LUT3
select -assert-max 6 t:LUT3
select -assert-max 8 t:LUT4
select -assert-count 5 t:MUXF5
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:MUXF5 %% t:* %D

5
tests/arch/xilinx/macc.ys
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@ -27,6 +27,5 @@ cd macc2 # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 1 t:FDRE
select -assert-count 1 t:LUT2
select -assert-count 40 t:LUT3
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D
select -assert-count 41 t:LUT2
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 %% t:* %D

11
tests/arch/xilinx/mux_lut4.ys
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@ -32,11 +32,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux8 # Constrain all select calls below inside the top module
select -assert-max 5 t:LUT1
select -assert-max 3 t:LUT3
select -assert-max 3 t:LUT4
select -assert-max 5 t:LUT4
select -assert-max 3 t:MUXF5
select -assert-count 1 t:MUXF6
select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D
select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
design -load read
@ -45,8 +44,10 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 32 t:LUT*
select -assert-max 34 t:LUT*
select -assert-max 16 t:MUXF5
select -assert-max 8 t:MUXF6
select -assert-max 4 t:MUXF7
select -assert-max 1 t:MUXF8
select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 %% t:* %D
select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 t:MUXF8 %% t:* %D

2
tests/techmap/shiftx2mux.ys
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@ -75,7 +75,7 @@ design -save gold
design -load gold
techmap
abc -lut 6
abc9 -lut 6
select -assert-count 16 t:$lut
design -stash gate