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abc: remove -lut/-luts

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This commit is contained in:
Lofty 2026-03-24 12:59:17 +00:00
parent 5fd39ff3e1
commit 3369cc525f
20 changed files with 35 additions and 118 deletions
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4
techlibs/anlogic/synth_anlogic.cc
View file

@ -193,7 +193,7 @@ struct SynthAnlogicPass : public ScriptPass
run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
run("abc9 -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))
@ -206,7 +206,7 @@ struct SynthAnlogicPass : public ScriptPass
if (check_label("map_luts"))
{
run("abc -lut 4:6");
run("abc9 -lut 4:6");
run("clean");
}

2
techlibs/efinix/synth_efinix.cc
View file

@ -196,7 +196,7 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_luts"))
{
run("abc -lut 4");
run("abc9 -lut 4");
run("clean");
}

4
techlibs/gatemate/synth_gatemate.cc
View file

@ -318,11 +318,11 @@ struct SynthGateMatePass : public ScriptPass
run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
}
if (!luttree || help_mode) {
std::string abc_args = " -dress -lut 4";
std::string abc_args = " -lut 4";
if (dff) {
abc_args += " -dff";
}
run("abc " + abc_args, "(without -luttree)");
run("abc9 " + abc_args, "(without -luttree)");
}
run("clean");
}

4
techlibs/lattice/synth_lattice.cc
View file

@ -544,14 +544,14 @@ struct SynthLatticePass : public ScriptPass
abc9_opts += " -dff";
run("abc9" + abc9_opts);
} else {
std::string abc_args = " -dress";
std::string abc_args = "";
if (nowidelut)
abc_args += " -lut 4";
else
abc_args += " -lut " + widelut_abc;
if (dff)
abc_args += " -dff";
run("abc" + abc_args);
run("abc9" + abc_args);
}
run("clean");
}

6
techlibs/nanoxplore/cells_sim.v
View file

@ -10,7 +10,6 @@ assign O = I1 ? s3[1] : s3[0];
endmodule
(* abc9_box, lib_whitebox *)
module NX_DFF(input I, CK, L, R, output reg O);
parameter dff_ctxt = 1'bx;
@ -36,7 +35,6 @@ always @(posedge clock, posedge async_reset)
endmodule
(* abc9_box, lib_whitebox *)
module NX_DFR(input I, CK, L, R, output O);
parameter data_inv = 1'b0;
@ -66,8 +64,6 @@ assign O = data_inv ? O_reg : ~O_reg;
endmodule
(* abc9_box, lib_whitebox *)
module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
parameter add_carry = 0;
@ -175,7 +171,6 @@ module NX_IOB_O(I, C, T, IO);
assign IO = C ? I : 1'bz;
endmodule
(* abc9_box, lib_whitebox *)
module NX_CY_1BIT(CI, A, B, S, CO);
(* abc9_carry *)
input CI;
@ -217,7 +212,6 @@ module NX_BFR(I, O);
assign O = data_inv ? ~I : I;
endmodule
(* abc9_box, lib_whitebox *)
module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3

3
techlibs/nanoxplore/cells_sim_u.v
View file

@ -1,4 +1,3 @@
(* abc9_box, lib_whitebox *)
module NX_GCK_U(SI1, SI2, CMD, SO);
input CMD;
input SI1;
@ -31,7 +30,6 @@ module NX_GCK_U(SI1, SI2, CMD, SO);
assign SO = inv_out ? ~SO_int : SO_int;
endmodule
(* abc9_box, lib_whitebox *)
module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
@ -205,7 +203,6 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
mem[WA] <= I[MEM_WIDTH-1:0];
endmodule
(* abc9_box, lib_whitebox *)
module NX_WFG_U(R, SI, ZI, SO, ZO);
input R;
input SI;

4
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -340,9 +340,9 @@ struct SynthNanoXplorePass : public ScriptPass
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k));
run("abc9" + abc9_opts);
} else {
std::string abc_args = " -dress";
std::string abc_args = "";
abc_args += " -lut 4";
run("abc" + abc_args);
run("abc9" + abc_args);
}
run("techmap -map +/nanoxplore/cells_map.v t:$lut");
run("opt -fast");

4
techlibs/xilinx/synth_xilinx.cc
View file

@ -640,7 +640,7 @@ struct SynthXilinxPass : public ScriptPass
if (flatten_before_abc)
run("flatten");
if (help_mode)
run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
run("abc9 -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
else if (abc9) {
if (lut_size != 6)
log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n");
@ -681,7 +681,7 @@ struct SynthXilinxPass : public ScriptPass
abc_opts += " -dff";
if (retime)
abc_opts += " -D 1";
run("abc" + abc_opts);
run("abc9" + abc_opts);
}
run("clean");