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Implemented much better #x select operator
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parent
efbb89de1a
commit
334fd03e1c
2 changed files with 91 additions and 16 deletions
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@ -121,6 +121,9 @@ namespace
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if (max_fanout > 0 && sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)] > max_fanout)
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continue;
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if (sel && !sel->selected(mod, chunk.wire))
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continue;
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if (sig_bit_ref.count(chunk) == 0) {
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bit_ref_t &bit_ref = sig_bit_ref[chunk];
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bit_ref.cell = cell->name;
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@ -308,9 +311,6 @@ struct ExtractPass : public Pass {
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log("integer value. Then this value is used to determine the order in which the pass\n");
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log("tries to map the modules to the design (ascending, default value is 0).\n");
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log("\n");
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log("This pass operates on whole modules or selected cells from modules. Other\n");
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log("selected entities (wires, etc.) are ignored.\n");
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log("\n");
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log("See 'help techmap' for a pass that does the opposite thing.\n");
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log("\n");
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}
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