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muxpack: reject slicing of predecessor Y ports in mux chain

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This commit is contained in:
Emil J. Tywoniak 2026-05-13 10:27:05 +02:00
parent 376d129df9
commit 334dd7b80c
3 changed files with 51 additions and 0 deletions
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10
tests/various/muxpack.v
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@ -238,6 +238,16 @@ module case_overlap (
end
endmodule
module chain_slice_self_input (
input [31:0] A,
input [1:0] S,
output [31:0] Y
);
wire [31:0] tmp;
assign tmp = S == 1 ? {A[7:0], A[7:0], A[7:0], A[7:0]} : A;
assign Y = S == 2 ? {A[15:0], tmp[15:0]} : tmp;
endmodule
module case_overlap2 (
input wire [2:0] x,
input wire a, b, c, d, e,

15
tests/various/muxpack.ys
View file

@ -249,6 +249,21 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top chain_slice_self_input
prep
design -save gold
muxpack
opt
#stat
select -assert-count 2 t:$mux
select -assert-count 0 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top case_overlap2
#prep # Do not prep otherwise $pmux's overlapping entry will get removed