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tests: Run async2sync before sat and/or sim to handle $check cells

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Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.
This commit is contained in:
Jannis Harder 2024-01-22 17:44:05 +01:00
parent 2baa578d94
commit 331ac5285f
41 changed files with 59 additions and 19 deletions
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3
tests/verilog/sign_array_query.ys
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@ -14,6 +14,7 @@ endmodule
EOT
prep -top top
async2sync
sim -n 3 -clock clk
design -reset
@ -32,6 +33,7 @@ endmodule
EOT
prep -top top
async2sync
sim -n 3 -clock clk
design -reset
@ -49,4 +51,5 @@ endmodule
EOT
prep -top top
async2sync
sim -n 3 -clock clk