mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-03 21:09:12 +00:00 
			
		
		
		
	tests: Run async2sync before sat and/or sim to handle $check cells
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
This commit is contained in:
		
							parent
							
								
									2baa578d94
								
							
						
					
					
						commit
						331ac5285f
					
				
					 41 changed files with 59 additions and 19 deletions
				
			
		| 
						 | 
				
			
			@ -2,4 +2,5 @@ read_verilog -sv prefix.sv
 | 
			
		|||
hierarchy
 | 
			
		||||
proc
 | 
			
		||||
select -module top
 | 
			
		||||
async2sync
 | 
			
		||||
sat -verify -seq 1 -prove-asserts -show-all
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue