tests: Run async2sync before sat and/or sim to handle $check cells

Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.

tests/verilog/asgn_expr.ys

@@ -1,3 +1,4 @@
 read_verilog -sv asgn_expr.sv
 proc
+async2sync
 sat -verify -prove-asserts -show-all

tests/verilog/atom_type_signedness.ys

@@ -14,6 +14,6 @@ always_comb begin
 end
 endmodule
 EOT
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 select -module dut
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/verilog/bug2042-sv.ys

@@ -17,6 +17,7 @@ output reg b
 endmodule
 EOT
 proc
+async2sync
 sat -verify -prove-asserts
 
 
@@ -42,6 +43,7 @@ output b, c
 endmodule
 EOT
 proc
+async2sync
 sat -verify -prove-asserts
 
 

tests/verilog/func_tern_hint.ys

@@ -1,4 +1,5 @@
 read_verilog -sv func_tern_hint.sv
 proc
 opt
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all

tests/verilog/func_upto.ys

@@ -3,5 +3,6 @@ hierarchy -top top
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -prove-asserts -enable_undef

tests/verilog/int_types.ys

@@ -3,5 +3,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/verilog/mem_bounds.ys

@@ -3,4 +3,5 @@ proc
 flatten
 opt -full
 select -module top
+async2sync
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef

tests/verilog/net_types.ys

@@ -2,4 +2,5 @@ read_verilog -sv net_types.sv
 hierarchy
 proc
 opt -full
+async2sync
 sat -verify -prove-asserts -show-all

tests/verilog/package_task_func.ys

@@ -1,4 +1,5 @@
 read_verilog -sv package_task_func.sv
 proc
 opt -full
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all

tests/verilog/param_no_default.ys

@@ -3,5 +3,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/verilog/parameters_across_files.ys

@@ -16,5 +16,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/verilog/past_signedness.ys

@@ -14,6 +14,7 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
 design -reset
@@ -32,4 +33,5 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk

tests/verilog/prefix.ys

@@ -2,4 +2,5 @@ read_verilog -sv prefix.sv
 hierarchy
 proc
 select -module top
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all

tests/verilog/sign_array_query.ys

@@ -14,6 +14,7 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
 design -reset
@@ -32,6 +33,7 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
 design -reset
@@ -49,4 +51,5 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk

tests/verilog/size_cast.ys

@@ -2,4 +2,5 @@ read_verilog -sv size_cast.sv
 proc
 opt -full
 select -module top
+async2sync
 sat -verify -prove-asserts -show-all

tests/verilog/struct_access.ys

@@ -1,4 +1,5 @@
 read_verilog -formal -sv struct_access.sv
 proc
 opt -full
+async2sync
 sat -verify -seq 1 -prove-asserts -show-all

tests/verilog/typedef_across_files.ys

@@ -19,5 +19,6 @@ EOF
 
 proc
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/verilog/typedef_legacy_conflict.ys

@@ -33,5 +33,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/verilog/unbased_unsized.ys

@@ -3,5 +3,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/verilog/unbased_unsized_shift.ys

@@ -3,5 +3,6 @@ hierarchy
 proc
 flatten
 opt -full
+async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/verilog/unreachable_case_sign.ys

@@ -12,6 +12,7 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk
 
 design -reset
@@ -29,5 +30,6 @@ endmodule
 EOT
 
 prep -top top
+async2sync
 sim -n 3 -clock clk