tests: Run async2sync before sat and/or sim to handle $check cells

Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.

tests/svtypes/enum_simple.ys

@@ -1,5 +1,5 @@
 
 read_verilog -sv enum_simple.sv
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all
 

tests/svtypes/struct_dynamic_range.ys

@@ -4,4 +4,5 @@ select -assert-count 2 t:$shift
 select -assert-count 2 t:$shiftx
 prep -top top
 flatten
+async2sync
 sat -enable_undef -verify -prove-asserts

tests/svtypes/typedef_initial_and_assign.ys

@@ -9,6 +9,6 @@ logger -expect warning "reg '\\var_18' is assigned in a continuous assignment" 1
 logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1
 
 read_verilog -sv typedef_initial_and_assign.sv
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 select -module top
-sat -verify -seq 1 -tempinduct -prove-asserts -show-all
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all

tests/svtypes/typedef_struct_port.ys

@@ -1,5 +1,5 @@
 read_verilog -sv typedef_struct_port.sv
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 select -module top
 sat -verify -seq 1 -tempinduct -prove-asserts -show-all
 select -module test_parser