tests: Run async2sync before sat and/or sim to handle $check cells

Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.

tests/sat/asserts.ys

@@ -1,3 +1,3 @@
 read_verilog -sv asserts.v
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts

tests/sat/asserts_seq.ys

@@ -1,5 +1,5 @@
 read_verilog -sv asserts_seq.v
-hierarchy; proc; opt
+hierarchy; proc; opt; async2sync
 
 sat -verify  -prove-asserts -tempinduct -seq 1 test_001
 sat -falsify -prove-asserts -tempinduct -seq 1 test_002

tests/sat/initval.ys

@@ -1,5 +1,5 @@
 read_verilog -sv initval.v
-proc;;
+proc; async2sync;;
 
 sat -seq 10 -prove-asserts
 

tests/sat/sizebits.ys

@@ -1,2 +1,2 @@
 read_verilog -sv sizebits.sv
-prep; sat -verify -prove-asserts
+prep; async2sync; sat -verify -prove-asserts