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Converting PRESENTATION_ExSyn

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Krystine Sherwin 2023-08-04 10:29:14 +12:00
parent 4b40372446
commit 330a2272da
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31 changed files with 442 additions and 517 deletions
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10
manual/PRESENTATION_ExSyn/proc_03.v
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@ -1,10 +0,0 @@
module test(input A, B, C, D, E,
output reg Y);
always @* begin
Y <= A;
if (B)
Y <= C;
if (D)
Y <= E;
end
endmodule