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Converting PRESENTATION_ExSyn

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Krystine Sherwin 2023-08-04 10:29:14 +12:00
parent 4b40372446
commit 330a2272da
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31 changed files with 442 additions and 517 deletions
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5
manual/PRESENTATION_ExSyn/abc_01.ys
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@ -1,5 +0,0 @@
read_verilog abc_01.v
read_verilog -lib abc_01_cells.v
hierarchy -check -top test
proc; opt; techmap
abc -dff -liberty abc_01_cells.lib;;